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power tool controller 8-bit flash mcu HT45F3630 revision: v1.00 date: ? a ??? 0 ?? ? 01 ? ? a ??? 0 ?? ? 01 ?
rev. 1.00 ? ? a ??? 0 ?? ? 01 ? rev. 1.00 ? ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu tale o contents featres 6 cpu featu ? es .............................................................................................................................. ? pe ? ip ? e ? al featu ? es ...................................................................................................................... ? gene?al des??iption ............................................................................................. 7 blo?k diag?am ...................................................................................................... 7 pin assignment ........... ......................................................................................... 8 pin des??iption .......... .......................................................................................... 8 absolute ?aximum ratings .............................................................................. 10 d.c. c?a?a?te?isti?s ........................................................................................... 10 a.c. c?a?a?te?isti?s ........................................................................................... 11 hirc c?a?a?te?isti?s ......................................................................................... 1? i ? c a.c. c?a?a?te?isti?s ... .................................................................................. 1? a/d conve?te? ele?t?i?al c?a?a?te?isti?s ........... .............................................. 1? lvd/lvr ele?t?i?al c?a?a?te?isti?s .................................................................. 1? refe?en?e voltage c?a?a?te?isti?s ........... ........................................................ 1? ove? cu??ent p?ote?tion ele?t?i?al c?a?a?te?isti?s ........................................ 14 hig? voltage output c?a?a?te?isti?s ............................................................... 15 powe?-on reset c?a?a?te?isti?s ........... ............................................................ 15 system a???ite?tu?e .......................................................................................... 1? clo ? king and pipelining .............................................................................................................. 1 ? p ? og ? am counte ? ........................................................................................................................ 17 sta ? k .......................................................................................................................................... 18 a ? it ? meti ? and logi ? unit C alu ................................................................................................ 18 flas? p?og?am ?emo?y ..................................................................................... 19 st ? u ? tu ? e ..................................................................................................................................... 19 spe ? ial ve ? to ? s .......................................................................................................................... 19 look-up table ............. ............................................................................................................... 19 table p ? og ? am example ............................................................................................................. ? 0 in ci ?? uit p ? og ? amming C icp .................................................................................................... ? 1 on c ? ip debug suppo ? t C ocds .............................................................................................. ?? data ?emo?y ...................................................................................................... ?? st ? u ? tu ? e .................................................................................................................................... ?? gene ? al pu ? pose data ? emo ? y ................................................................................................. ?? spe ? ial pu ? pose data ? emo ? y .................................................................................................. ??
rev. 1.00 ? ?a??? 0?? ?01? rev. 1.00 ? ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu eial fntion eister esrition 4 indi ? e ? t add ? essing registe ? s C iar0 ? iar1 ? iar ? .................................................................... ? 4 ? emo ? y pointe ? s C ? p0 ? ? p1l ? ? p1h ? ? p ? l ? ? p ? h .............................................................. ? 4 a ?? umulato ? C acc ................................................................................................................... ? 5 p ? og ? am counte ? low registe ? C pcl ...................................................................................... ?? look-up table registe ? s C tblp ? tbhp ? tblh ......................................................................... ?? status registe ? C status ........................................................................................................ ?? eepro? data ?emo?y ........... ........................................................................... ?8 eepro ? data ? emo ? y st ? u ? tu ? e ............................................................................................. ? 8 eepro ? registe ? s ............ ....................................................................................................... ? 8 reading data f ? om t ? e eepro ? .............................................................................................. ? 0 w ? iting data to t ? e eepro ? ..................................................................................................... ? 0 w ? ite p ? ote ? tion .......................................................................................................................... ? 0 eepro ? inte ?? upt ............. ........................................................................................................ ? 0 p ? og ? amming conside ? ations ............. ........................................................................................ ? 1 os?illato?s .......... ................................................................................................ ?? os ? illato ? ove ? view ............. ...................................................................................................... ?? system clock confgurations ..................................................................................................... ?? inte ? nal rc os ? illato ? C hirc ............. ....................................................................................... ?? inte ? nal ?? khz os ? illato ? C lirc ............................................................................................... ?? ope?ating ?odes and system clo?ks ............................................................. ?? system clo ? ks ........................................................................................................................... ?? system ope ? ation ? odes .......................................................................................................... ? 4 cont ? ol registe ? ......................................................................................................................... ?? ope ? ating ? ode swit ?? ing ........................................................................................................ ? 7 standby cu ?? ent conside ? ations ............................................................................................... 41 wake-up .................................................................................................................................... 41 wat??dog time? ........... ...................................................................................... 4? wat ?? dog time ? clo ? k sou ?? e ................................................................................................... 4 ? wat ?? dog time ? cont ? ol registe ? ............. ................................................................................. 4 ? wat ?? dog time ? ope ? ation ........................................................................................................ 4 ? reset and initialisation ..................................................................................... 44 reset fun ? tions ............. ............................................................................................................ 44 reset initial conditions ............................................................................................................. 4 ? input/output po?ts ............................................................................................ 49 pull- ? ig ? resisto ? s ..................................................................................................................... 49 po ? t a wake-up ............. ............................................................................................................. 50 i/o po ? t cont ? ol registe ? s .......................................................................................................... 50 i/o po ? t sou ?? e cu ?? ent cont ? ol ................................................................................................. 51 pin-s ? a ? ed fun ? tions ............. .................................................................................................... 5 ? i/o pin st ? u ? tu ? es ....................................................................................................................... 54 p ? og ? amming conside ? ations ............. ....................................................................................... 55
rev. 1.00 4 ? a ??? 0 ?? ? 01 ? rev. 1.00 5 ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu tier moles tm 55 int ? odu ? tion ................................................................................................................................ 55 t ? ope ? ation ............. ................................................................................................................ 55 t ? clo ? k sou ?? e ............. ........................................................................................................... 5 ? t ? inte ?? upts .............................................................................................................................. 5 ? t ? exte ? nal pins ....................................................................................................................... 5 ? t ? input/output pin sele ? tion ................................................................................................... 5 ? p ? og ? amming conside ? ations ............. ........................................................................................ 57 pe?iodi? type t? C pt? ................................................................................... 58 pe ? iodi ? t ? ope ? ation ............. ................................................................................................. 58 pe ? iodi ? type t ? registe ? des ?? iption ..................................................................................... 58 pe ? iodi ? type t ? ope ? ating ? odes .......................................................................................... ?? analog to digital conve?te? .......... ................................................................... 7? a/d conve ? te ? ove ? view ............................................................................................................ 7 ? a/d conve ? te ? registe ? des ?? iption ........................................................................................... 7 ? a/d conve ? te ? data registe ? s C sadol ? sadoh ............. ........................................................ 7 ? a/d conve ? te ? cont ? ol registe ? s C sadc0 ? sadc1 .................................................................. 7 ? a/d conve ? te ? ope ? ation ........................................................................................................... 7 ? a/d conve ? te ? refe ? en ? e voltage .............................................................................................. 77 a/d conve ? te ? input signals ....................................................................................................... 77 conve ? sion rate and timing diag ? am ....................................................................................... 78 summa ? y of a/d conve ? sion steps ............. .............................................................................. 78 p ? og ? amming conside ? ations ............. ........................................................................................ 79 a/d conve ? sion fun ? tion ............. .............................................................................................. 80 a/d conve ? sion p ? og ? amming examples ............. ...................................................................... 80 ove? cu??ent p?ote?tion .................................................................................... 8? ove ? cu ?? ent p ? ote ? tion ope ? ation ............................................................................................ 8 ? ove ? cu ?? ent p ? ote ? tion cont ? ol registe ? s ................................................................................ 8 ? input voltage range ................................................................................................................... 8 ? offset calib ? ation ....................................................................................................................... 8 ? hig? voltage output .......... ................................................................................ 87 fun ? tional des ?? iption ................................................................................................................ 88 p ? ote ? tion ? e ?? anism ............. ................................................................................................... 88 cont ? ol registe ? s ....................................................................................................................... 88 i ? c inte?fa?e ........................................................................................................ 89 i ? c inte ? fa ? e ope ? ation .............................................................................................................. 89 i ? c registe ? s .............................................................................................................................. 91 i ? c bus communi ? ation ............................................................................................................ 94 i ? c bus sta ? t signal ................................................................................................................... 95 slave add ? ess ........................................................................................................................... 95 i ? c bus read/w ? ite signal ........................................................................................................ 95 i ? c bus slave add ? ess a ? knowledge signal ............................................................................. 95 i ? c bus data and a ? knowledge signal ............ ......................................................................... 9 ? i ? c time-out cont ? ol ................................................................................................................... 97
rev. 1.00 4 ?a??? 0?? ?01? rev. 1.00 5 ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu nterrts 8 inte ?? upt registe ? s ...................................................................................................................... 98 inte ?? upt ope ? ation ................................................................................................................... 10 ? exte ? nal inte ?? upt ............. ......................................................................................................... 104 ove ? cu ?? ent p ? ote ? tion inte ?? upt ............................................................................................. 105 time base inte ?? upts ................................................................................................................ 105 i ? c inte ?? upt ............. ................................................................................................................. 107 a/d conve ? te ? inte ?? upt ............................................................................................................ 107 lvd inte ?? upt ............................................................................................................................ 107 eepro ? inte ?? upt ............. ...................................................................................................... 107 ? ulti-fun ? tion inte ?? upt ............................................................................................................. 108 t ? inte ?? upts ............................................................................................................................ 108 inte ?? upt wake-up fun ? tion ...................................................................................................... 108 p ? og ? amming conside ? ations ............. ...................................................................................... 109 low voltage dete?to? C lvd .......... ................................................................. 110 lvd registe ? ............. ............................................................................................................... 110 lvd ope ? ation .......................................................................................................................... 111 appli?ation ci??uits ........... .............................................................................. 11? inst?u?tion set .................................................................................................. 11? int ? odu ? tion .............................................................................................................................. 11 ? inst ? u ? tion timing ..................................................................................................................... 11 ? ? oving and t ? ansfe ?? ing data .................................................................................................. 11 ? a ? it ? meti ? ope ? ations ............................................................................................................... 11 ? logi ? al and rotate ope ? ation .................................................................................................. 114 b ? an ?? es and cont ? ol t ? ansfe ? ................................................................................................ 114 bit ope ? ations .......................................................................................................................... 114 table read ope ? ations ............................................................................................................ 114 ot ? e ? ope ? ations ............. ......................................................................................................... 114 inst?u?tion set summa?y .......... ...................................................................... 115 table conventions .................................................................................................................... 115 extended inst ? u ? tion set ............. ............................................................................................. 117 instruction defnition extended instruction defnition ................................................................................................ 1 ? 8 pa?kage info?mation ....................................................................................... 1?5 1 ? -pin ssop (150mil) outline dimensions .............................................................................. 1 ??
rev. 1.00 ? ? a ??? 0 ?? ? 01 ? rev. 1.00 7 ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu featres cpu featres ? operating voltage v cc : 12v (maximum) f sys =8mhz: 2.2v~5.5v ? up to 0.5 s instruction cycle with 8mhz system clock at v dd =5v ? power down and wake-up functions to reduce power consumption ? oscillator type internal high speed rc C hirc internal low speed 32khz rc C lirc ? multi-mode operation: normal, slow, idle and sleep ? fully integrated internal 8mhz oscillator requires no external components ? all instructions executed in 1~3 instruction cycles ? table read instructions ? 115 powerful instructions ? 6-level subroutine nesting ? bit manipulation instruction ? flash program memory: 2k16 ? ram data memory: 648 ? eeprom memory: 328 ? watchdog t imer function ? 12 bidirectional i/o lines ? programmable i/o port source current for led applications ? dual pin-shared external interrupts ? over current protection (ocp) function with interrupt ? high v oltage output (hvo) function ? level shift function ? multiple t imer modules for time measure, input capture, compare matc h output, pwm output or single pulse output function ? dual t ime-base functions for generation of fxed time interrupt signals ? 8-channel 12-bit resolution a/d converter ? i 2 c interface ? low voltage reset function ? low voltage detect function ? flash program memory can be re-programmed up to 100,000 times ? flash program memory data retention > 10 years ? eeprom data memory can be re-programmed up to 1,000,000 times ? eeprom data memory data retention > 10 years ? package type: 16-pin ssop
rev. 1.00 ? ?a??? 0?? ?01? rev. 1.00 7 ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu eneral esrition the device is a flash memory a/d type 8-bit high performance risc architecture microcontroller with a high voltage driver of up to 12v , which is specifically designed for power tool controller applications. of fering users the convenience of fl ash mem ory mul ti-programming feat ures, thi s device also includ es a wide range of functions and features. other memory includes an area of ram data memory as well as an area of eeprom memory for storage of non-volatile data such as serial numbers, calibration data etc. analog fea tures include a multi-cha nnel 12-bit a/d converte r, an over curre nt protection funct ion and a l evel shi ft funct ion. mul tiple and ext remely fle xible t imer modul es provide t iming, pulse generation and pwm generation functions. easy communication with the outside world is provided using the internal fully integrated i 2 c interface, this popular interface which provides designers with a means of easy communicatio n with external peripheral hardware. protective features such as an internal w atchdog t imer, low v oltage reset and low v oltage detector coupled with excellent noise imm unity and esd protection ensure that reliable operation is maintained in hostile electrical environments. a fu ll c hoice of va rious i nternal hi gh a nd l ow osc illator fu nctions i s pr ovided i ncluding a fu lly integrated system oscillator which requires no external components for its implementation. the ability t o opera te a nd swi tch dyna mically be tween a ra nge of opera ting m odes usi ng di fferent clock sources gives users the ability to optimise microcontroller operation and minimise power consumption. this device conta ins a programmab le i/o port source current function which is used to implement led driving function. also the incl usion of fexible i/o programming features, t ime-base functions along with many other features further enhance device functionality and fexibility for wide range of application possibilities. 8-bit risc ?cu co?e time? ?odules flas? p?og?am ?emo?y eepro? data ?emo?y flas?/eepro? p?og?amming ci??uit?y (ocds/icp) ra? data ?emo?y time bases level s?ift low voltage dete?t low voltage dete?t wat??dog time? ove? cu??ent p?ote?tion hvo vcc 1?-bit a/d conve?te? i ? c i/o reset ci??uit inte??upt cont?olle? inte?nal rc os?illato?s
rev. 1.00 8 ? a ??? 0 ?? ? 01 ? rev. 1.00 9 ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu pin ssinent HT45F3630ht453630 6 p- hvo vcc vdd/avdd pa1/ocpi/ptck0/ptp0b/an1 pa7/an7/ptp1i pa?/an?/ptck1 vss/avss/vssh pa5/an5 pa4/an4/int0 pa?/vref/an? pa?/icpck/ptp0 i/an?/ocdsck pa0/icpda/ptp0/an0/ocdsda pb0/int1/ptp1 pb1/ptp1b pb?/sda pb?/scl 1? 15 14 1? 1? 11 10 9 1 ? ? 4 5 ? 7 8 note: 1. if the pin-shared pin functions have multiple outputs simultane ously, the desired pin-shared function is determined by the corresponding software control bits. 2. the ocdsda and ocdsck pins are supplied for the ocds dedicated pins and as such only available for the ht45v3630 device which is the ocds ev chip for the HT45F3630 device. with the exception of the power pins and some relevant transformer control pins, all pins on the device can be referenced by their port name, e.g. p a0, p a1 etc., which refer to the digital i/o function of the pins. however these port pins are also shared with other function such as the analog to digital converter, t imer module pins etc. t he function of each pin is listed in the following table, however the details behind how each pin is confgured is contained in other sections of the datasheet. pa0/icpda/ptp0/ an0/ocdsda pa0 papu pawu pas0 st c ? os gene ? al pu ? pose i/o. registe ? enabled pull-up and wake-up. icpda st c ? os icp add ? ess/data ptp0 pas0 c ? os pt ? 0 output an0 pas0 an adc input ?? annel 0 ocdsda st c ? os ocds add ? ess/data - fo ? ev ?? ip only. pa1/ocpi/ptck0/ ptp0b/an1 pa1 papu pawu pas0 st c ? os gene ? al pu ? pose i/o. registe ? enabled pull-up and wake-up. ocpi pas0 an ocp input ptck0 pas0 st pt ? 0 ? lo ? k input ptp0b pas0 c ? os pt ? 0 inve ? ting output an1 pas0 an adc input ?? annel 1 pa ? /ocdsck/ icpck/ptp0i/an ? pa ? papu pawu pas0 st c ? os gene ? al pu ? pose i/o. registe ? enabled pull-up and wake-up. ocdsck st ocds ? lo ? k - fo ? ev ?? ip only. icpck st icp ? lo ? k ptp0i pas0 st pt ? 0 ? aptu ? e input an ? pas0 an adc input ?? annel ? pa ? /vref/an ? pa ? papu pawu pas0 st c ? os gene ? al pu ? pose i/o. registe ? enabled pull-up and wake-up. vref pas0 an adc and ocp (dac) ? efe ? en ? e voltage input an ? pas0 an adc input ?? annel ?
rev. 1.00 8 ?a??? 0?? ?01? rev. 1.00 9 ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu pin ae fntion pt t t esritions pa4/an4/int0 pa4 papu pawu pas1 st c ? os gene ? al pu ? pose i/o. registe ? enabled pull-up and wake-up. up. an4 pas1 an adc input ?? annel 4 int0 pas1 integ intc0 st exte ? nal inte ?? upt 0 input pa5/an5 pa5 papu pawu pas1 st c ? os gene ? al pu ? pose i/o. registe ? enabled pull-up and wake-up. an5 pas1 an adc input ?? annel 5 pa ? /an ? /ptck1 pa ? papu pawu pas1 st c ? os gene ? al pu ? pose i/o. registe ? enabled pull-up and wake-up. an ? pas1 an adc input ?? annel ? ptck1 pas1 st pt ? 1 ? lo ? k input pa7/an7/ptp1i pa7 papu pawu pas1 st c ? os gene ? al pu ? pose i/o. registe ? enabled pull-up and wake-up. an7 pas1 an adc input ?? annel 7 ptp1i pas1 st pt ? 1 ? aptu ? e input pb0/int1/ptp1 pb0 pbpu pbs0 st c ? os gene ? al pu ? pose i/o. registe ? enabled pull-up. int1 pbs0 integ intc0 st exte ? nal inte ?? upt 1 input ptp1 pbs0 c ? os pt ? 1 output pb1/ptp1b pb1 pbpu pbs0 st c ? os gene ? al pu ? pose i/o. registe ? enabled pull-up. ptp1b pbs0 c ? os pt ? 1 inve ? ting output pb ? /sda pb ? pbpu pbs0 st c ? os gene ? al pu ? pose i/o. registe ? enabled pull-up. sda pbs0 st n ? os i ? c data line pb ? /scl pb ? pbpu pbs0 st c ? os gene ? al pu ? pose i/o. registe ? enabled pull-up. scl pbs0 st n ? os i ? c ? lo ? k line hvo hvo pwr level s ? ift output vcc vcc pwr level s ? ift positive powe ? input vdd/avdd* vdd pwr digital positive powe ? supply avdd pwr analog positive powe ? supply vss/avss/vssh** vss pwr digital negative powe ? supply avss pwr analog negative powe ? supply vssh pwr hig ? voltage devi ? e negative powe ? supply legend: i/t: input type; o/t: output type; opt: optional by register option; pwr: power; st: schmitt t rigger input; cmos: cmos output; nmos: nmos output; an: analog signal; *: vdd is the device power supply while a vdd is the adc power supply . the a vdd pin is bonded together internally with vdd. **: vss is the device ground pin while a vss is the adc ground pin and vssh is the high voltage device ground pin. the a vss pin and vssh pin are bonded together internally with vss.
rev. 1.00 10 ? a ??? 0 ?? ? 01 ? rev. 1.00 11 ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu solte mai atins supply v oltage for v cc .............. .......................................................................................... v dd to 12v supply v oltage for v dd ....................................................................................... v ss -0.3v to v ss +6.0v input v oltage .............. ....................................................................................... v ss -0.3v to v dd +0.3v storage t emperature ............... ....................................................................................... -50c to 125 c operating t emperature .............. ...................................................................................... -40c to 85 c i ol t otal .............. ................................................................................................... ....................... 80ma i oh t otal .............. ......................................................................................................................... -80ma total power dissipation .............. .............................................................................................. 500mw note: these are stress ratings only . stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specifcation is not implied and prolonged exposure to extreme conditions may affect device reliability. ta= ? 5c symbol pa?amete? test conditions ?in. typ. ?ax. unit v dd conditions v dd ope ? ating voltage (hirc) f sys =f hirc =8 ? hz ? . ? 5.5 v v dd ope ? ating voltage (lirc) f sys =f lirc = ?? khz ? . ? 5.5 v i dd ope ? ating cu ?? ent (hirc) ? v no load ? all pe ? ip ? e ? als off ? f sys =f hirc =8 ? hz 0.8 1. ? ma 5v 1. ? ? .4 ma ope ? ating cu ?? ent (lirc) ? v no load ? all pe ? ip ? e ? als off ? f sys =f lirc = ?? khz 10 ? 0 5v ? 0 50 i stb standby cu ?? ent (sleep ? ode) ? v no load ? all pe ? ip ? e ? als off ? wdt off 0. ? 0.8 5v 0.5 1 standby cu ?? ent (sleep ? ode) ? v no load ? all pe ? ip ? e ? als off ? wdt on 1.5 ? 5v ? 5 standby cu ?? ent (idle0 ? ode) ? v no load ? all pe ? ip ? e ? als off ? f sub on ? 5 5v 5 10 standby cu ?? ent (idle1 ? ode ? hirc) ? v no load ? all pe ? ip ? e ? als off ? f sub on ? f sys =f hirc =8 ? hz ?? 0 500 5v ? 00 800 i oh sou ?? e cu ?? ent fo ? i/o po ? ts ? v v oh =0.9v dd ? sledc[m+1 ? m] =00b (m=0 o ? ? o ? 4 ) -0.7 1.5 ma 5v v oh =0.9v dd ? sledc[m+1 ? m] =00b (m=0 o ? ? o ? 4 ) -1.5 ? .9 ma ? v v oh =0.9v dd ? sledc[m+1 ? m] =01b (m=0 o ? ? o ? 4 ) -1. ? ? .5 ma 5v v oh =0.9v dd ? sledc[m+1 ? m] =01b (m=0 o ? ? o ? 4 ) - ? .5 5.1 ma ? v v oh =0.9v dd ? sledc[m+1 ? m] =10b (m=0 o ? ? o ? 4 ) -1.8 ? . ? ma 5v v oh =0.9v dd ? sledc[m+1 ? m] =10b (m=0 o ? ? o ? 4 ) - ? . ? 7. ? ma ? v v oh =0.9v dd ? sledc[m+1 ? m] = 11b (m=0 o ? ? o ? 4 ) -4.0 8 ma 5v v oh =0.9v dd ? sledc[m+1 ? m] = 11b (m=0 o ? ? o ? 4 ) -8.0 1 ? ma
rev. 1.00 10 ?a??? 0?? ?01? rev. 1.00 11 ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu ol paraeter test conitions min t ma unit conitions v il input low voltage fo ? i/o po ? ts 5v 0 1.5 v 0 0. ? v dd v v ih input hig ? voltage fo ? i/o po ? ts 5v ? .5 5 v 0.8v dd v dd v i ol sink cu ?? ent fo ? i/o po ? t ? v v ol =0.1v dd 1 ? ?? ma 5v v ol =0.1v dd ?? ? 4 ma r ph pull- ? ig ? resistan ? e fo ? i/o po ? ts ? v ? 0 ? 0 100 k 5v 10 ? 0 50 k i leak input leakage cu ?? ent 5v v in =v dd o ? v in =v ss 1 a v oh output hig ? voltage fo ? i/o po ? ts ? v i oh =-5.5ma ? .7 v 5v i oh =-11ma 4.5 v v ol output low voltage fo ? i/o po ? ts ? v i ol =1 ? ma 0. ? v 5v i ol = ?? ma 0.5 v a.c. c?a?a?te?isti?s ta= ? 5c symbol pa?amete? test conditions ?in. typ. ?ax. unit v dd conditions f sys system clo ? k (lirc) ? . ? v~ 5.5v f sys =f lirc = ?? khz ?? khz f lirc low speed inte ? nal rc os ? illato ? (lirc) ? v ta= ? 5c -10% ?? +10% khz 5v ta= ? 5c -10% ?? +10% khz t rstd system reset delay time (powe ? -on reset ? lvr ha ? dwa ? e reset ? lvr softwa ? e reset ? wdt softwa ? e reset) ? 5 50 100 ms system reset delay time (wdt time-out ha ? dwa ? e cold reset) 8. ? 1 ? .7 ?? . ? ms t sst system sta ? t-up time ? pe ? iod (wake-up f ? om powe ? down ? ode and f sys off) f sys =f hirc ~f hirc / ? 4 1 ? t hirc f sys =f lirc ? t lirc system sta ? t-up time ? pe ? iod (slow mode ? normal mode) f hirc off on (hircf=1) 1 ? t hirc system sta ? t-up time ? pe ? iod (wake-up f ? om powe ? down ? ode and f sys on) f sys =f hirc ~f hirc / ? 4 ? t hirc f sys =f lirc ? t lirc system sta ? t-up time ? pe ? iod (wdt time-out ha ? dwa ? e cold reset) 0 t h t int exte ? nal inte ?? upt ? inimum pulse widt ? 10 s t tck ptckn input pin ? inimum pulse widt ? 0. ? s t tpi ptpni input pin ? inimum pulse widt ? 0. ? s t eerd eepro ? ? ead time 4 t sys t eewr eepro ? w ? ite time ? 4 ms
rev. 1.00 1 ? ? a ??? 0 ?? ? 01 ? rev. 1.00 1? ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu hc charateristis f ? equen ? y a ?? u ? a ? y t ? immed at v dd = ? v symbol pa?amete? test conditions ?in. typ. ?ax. unit v dd conditions f hirc hig ? speed inte ? nal rc os ? illato ? (hirc) ? v ta= ? 5c - ? % 8 + ? % ? hz ? v ta=0c ~ 70c -5% 8 +5% ? hz ? . ? v~5.5v ta=0c ~ 70c -7% 8 +7% ? hz ? . ? v~5.5v ta=-40c ~ 85c -10% 8 +10% ? hz f ? equen ? y a ?? u ? a ? y t ? immed at v dd =5v symbol pa?amete? test conditions ?in. typ. ?ax. unit v dd conditions f hirc hig ? speed inte ? nal rc os ? illato ? (hirc) 5v ta= ? 5c - ? % 8 + ? % ? hz 5v ta=0c ~ 70c -5% 8 +5% ? hz ? . ? v~5.5v ta=0c ~ 70c -7% 8 +7% ? hz ? . ? v~5.5v ta=-40c ~ 85c -10% 8 +10% ? hz i ? c a.c. c?a?a?te?isti?s ta= ? 5c symbol pa?amete? test conditions ?in. typ. ?ax. unit v dd conditions f i ? c i ? c standa ? d ? ode (100khz) f sys f ? equen ? y no ? lo ? k deboun ? e ? ? hz ? system ? lo ? k deboun ? e 4 ? hz 4 system ? lo ? k deboun ? e 8 ? hz i ? c fast ? ode (400khz) f sys f ? equen ? y no ? lo ? k deboun ? e 5 ? hz ? system ? lo ? k deboun ? e 10 ? hz 4 system ? lo ? k deboun ? e ? 0 ? hz a/d conve?te? ele?t?i?al c?a?a?te?isti?s ta= ? 5c symbol pa?amete? test conditions ?in. typ. ?ax. unit v dd conditions v dd ope ? ating voltage ? .7 5.5 v v adi input voltage 0 v ref v v ref refe ? en ? e voltage ? v dd v dnl diffe ? ential nonlinea ? ity ? v v ref =v dd ? t adck =0.5s ? lsb 5v v ref =v dd ? t adck =0.5s ? v v ref =v dd ? t adck =10s 5v v ref =v dd ? t adck =10s inl integ ? al nonlinea ? ity ? v v ref =v dd ? t adck =0.5s 4 lsb 5v v ref =v dd ? t adck =0.5s ? v v ref =v dd ? t adck =10s 5v v ref =v dd ? t adck =10s i adc additional cu ?? ent fo ? a/d conve ? te ? enable ? v no load ? t adck =0.5s 1 ? ma 5v no load ? t adck =0.5s 1.5 ? ma t adck clo ? k pe ? iod 0.5 10 s t on ? st a/d conve ? te ? on-to-sta ? t time 4 s t ads sampling time 4 t adck t adc conve ? sion time (in ? lude a/d sample and hold time) 1 ? t adck
rev. 1.00 1? ?a??? 0?? ?01? rev. 1.00 1 ? ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu letrial charateristis ta= ? 5c symbol pa?amete? test conditions ?in. typ. ?ax. unit v dd conditions v lvr low voltage reset voltage lvr enable ? voltage sele ? t ? .1v -5% ? .1 +5% v lvr enable ? voltage sele ? t ? .55v -5% ? .55 +5% lvr enable ? voltage sele ? t ? .15v -5% ? .15 +5% lvr enable ? voltage sele ? t ? .8v -5% ? .8 +5% v lvd low voltage dete ? tion voltage lvd enable ? voltage sele ? t ? .0v -5% ? .0 +5% v lvd enable ? voltage sele ? t ? . ? v -5% ? . ? +5% lvd enable ? voltage sele ? t ? .4v -5% ? .4 +5% lvd enable ? voltage sele ? t ? .7v -5% ? .7 +5% lvd enable ? voltage sele ? t ? .0v -5% ? .0 +5% lvd enable ? voltage sele ? t ? . ? v -5% ? . ? +5% lvd enable ? voltage sele ? t ? . ? v -5% ? . ? +5% lvd enable ? voltage sele ? t 4.0v -5% 4.0 +5% i lvrlvdbg ope ? ating cu ?? ent ? v lvd enable ? lvr enable ? vbgen=0 15 a 5v lvd enable ? lvr enable ? vbgen=0 ? 0 ? 5 a ? v lvd enable ? lvr enable ? vbgen=1 150 a 5v lvd enable ? lvr enable ? vbgen=1 180 ? 00 a t lvds lvdo stable time fo ? lvr enable ? vbgen=0 ? lvd off on 15 s fo ? lvr disable ? vbgen=0 ? lvd off on 150 s i lvr additional cu ?? ent fo ? lvr enable lvd disable ? vbgen=0 tbd a i lvd additional cu ?? ent fo ? lvd enable lvr disable ? vbgen=0 tbd a ta= ? 5c symbol pa?amete? test conditions ?in. typ. ?ax. unit v dd conditions v bg bandgap refe ? en ? e voltage -5% 1.04 +5% v t bgs v bg tu ? n on stable time no load 150 s i bg additional cu ?? ent fo ? bandgap refe ? en ? e enable lvr disable ? lvd disable tbd a note the v bg yod v vg dv yuu udo vdo s
rev. 1.00 14 ? a ??? 0 ?? ? 01 ? rev. 1.00 15 ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu er crrent protetion letrial charateristis ta= ? 5c symbol pa?amete? test conditions ?in. typ. ?ax. unit v dd conditions i ocp ope ? ating cu ?? ent ? v ocpen[1:0]=01b ? dac v ref = ? .5v ?? 5 a 5v ocpen[1:0]=01b ? dac v ref = ? .5v 7 ? 0 1 ? 50 a v os_c ? p compa ? ato ? input offset voltage ? v wit ? out ? alib ? ation (ocpcof[4:0]=10000b) -15 15 mv 5v wit ? out ? alib ? ation (ocpcof[4:0]=10000b) -15 15 mv ? v wit ? ? alib ? ation -4 4 mv 5v wit ? ? alib ? ation -4 4 mv v hys hyste ? esis ? v ? 0 40 ? 0 mv 5v ? 0 40 ? 0 mv v c ? _c ? p compa ? ato ? common ? ode voltage range ? v v ss v dd -1.4 v 5v v ss v dd -1.4 v v os_opa opa input offset voltage ? v wit ? out ? alib ? ation (ocpoof[5:0]=100000b) -15 15 mv 5v wit ? out ? alib ? ation (ocpoof[5:0]=100000b) -15 15 mv ? v wit ? ? alib ? ation -4 4 mv 5v wit ? ? alib ? ation -4 4 mv v c ? _opa opa common ? ode voltage range ? v v ss v dd -1.4 v 5v v ss v dd -1.4 v v or opa ? aximum output voltage range ? v v ss +0.1 v dd -0.1 v 5v v ss +0.1 v dd -0.1 v ga pga gain a ?? u ? a ? y ? v all gain -5 5 % 5v all gain -5 5 % dnl diffe ? ential nonlinea ? ity ? v dac v ref =v dd 1 lsb 5v dac v ref =v dd 1 lsb inl integ ? al nonlinea ? ity ? v dac v ref =v dd 1.5 lsb 5v dac v ref =v dd 1.5 lsb
rev. 1.00 14 ?a??? 0?? ?01? rev. 1.00 15 ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu hih oltae tt charateristis ta= ? 5c symbol pa?amete? test conditions ?in. typ. ?ax. unit v dd conditions v in input voltage v dd 1 ? v i oh sou ?? e cu ?? ent fo ? hvo pin v oh =0.9 v in ? v in =10v -100 ma i ol sink cu ?? ent fo ? hvo pin v ol =0.1 v in ? v in =10v 100 ma t r hvo output rising time v in =10v 0.5 s t f hvo output falling time v in =10v 0.5 s ta= ? 5c symbol pa?amete? test conditions ?in. typ. ?ax. unit v dd conditions v por v dd sta ? t voltage to ensu ? e powe ? -on reset 100 mv rr por v dd raising rate to ensu ? e powe ? -on reset 0.0 ? 5 v/ms t por ? inimum time fo ? v dd stays at v por to ensu ? e powe ? -on reset 1 ms v dd t por rr por v por time
rev. 1.00 1 ? ? a ??? 0 ?? ? 01 ? rev. 1.00 17 ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu ste rhitetre a key factor in the high-performanc e features of the holtek range of microcontrollers is attributed to their inte rnal system architecture. the range of the device take advantag e of the usual features found within ris c microcontrollers providing increas ed s peed of operation and enhanced performance. the pi pelining sc heme i s i mplemented i n suc h a wa y t hat i nstruction fe tching a nd i nstruction execution are overlapped, hence instructions are ef fectively executed in one or two cycles for most of the standard or extended instructions respectively . the exceptions to this are branch or call instructions which need one more cycle. an 8-bit wide alu is used in practically all instruction set operations, which carries out arithm etic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the internal data path is simplifed by moving data through the accumulator and the alu. certain internal registers are implemented in the data memory and can be directly or indirectly addresse d. the simple addressi ng met hods of these registers along with additi onal architectural features ensure that a minimum of external components is required to provide a functional i/o and a/d control system with maximum reliability and flexibility . this makes the device suitable for low-cost, high-volume production for controller applications. the main system clock, derived from either a hirc or lirc oscillator is subdivided into four internally generated non-overlapping clocks, t1~t4. the program counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way , one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructio ns takes place in consecutive instruction c ycles, t he pi pelining st ructure of t he m icrocontroller e nsures t hat i nstructions a re effectively executed in one instruction cycle. the exception to this are instructions where the contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. fet?? inst. (pc+?) exe?ute inst. (pc+1) os?illato? clo?k (system clo?k) p?ase clo?k t1 p?ase clo?k t? p?ase clo?k t? p?ase clo?k t4 p?og?am counte? pipelining pc pc+1 pc+? fet?? inst. (pc+1) exe?ute inst. (pc) exe?ute inst. (pc-1) fet?? inst. (pc) system clo?king and pipelining
rev. 1.00 1? ?a??? 0?? ?01? rev. 1.00 17 ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu for instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. an extra cycle is required as the program takes one cycle t o frst obt ain t he a ctual j ump or c all a ddress a nd t hen a nother c ycle t o a ctually e xecute t he branch. the requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. fet?? inst. 1 1 ?ov a?[1?h] ? call delay ? cpl [1?h] 4 : 5 : ? delay: nop exe?ute inst. 1 fet?? inst. ? exe?ute inst. ? fet?? inst. ? flus? pipeline fet?? inst. ? exe?ute inst. ? fet?? inst. 7 inst?u?tion fet??ing p?og?am counte? during pro gram e xecution, t he progr am co unter i s use d t o ke ep t rack of t he a ddress of t he next instruction to be executed. it is automatically incremented by one each time an instruction is executed except for instructions, such as jm p or call that demands a jump to a non- consecutive program memory address. only the lower 8 bits, known as the program counter low register, are directly addressable by the application program. when executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the program counter . for conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. pc10~pc8 pcl7~pcl0 p?og?am counte? the lower byte of the program counter , known as the program counter low register or pcl, is available for program control and is a readable and writeable register . by transferring data directly into t his r egister, a sh ort p rogram j ump c an b e e xecuted d irectly; h owever, a s o nly t his l ow b yte is available for manipulation, the jumps are limited to the present page of memory that is 256 locations. when such program jumps are executed it should also be noted that a dummy cycle will be inserted. manipulating the pcl register may cause program branching, so an extra cycle is needed to pre-fetch.
rev. 1.00 18 ? a ??? 0 ?? ? 01 ? rev. 1.00 19 ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu ta this is a special part of the memory which is used to save the contents of the program counter only. the stack is or ganized into 6 levels and neither part of the data nor part of the program space, and is neither readable nor writeable. the activated level is indexed by the stack pointer , and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction, ret or reti, the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack. if the stack is full and an enabled interrupt takes place, the interrupt request fag will be recorded but the acknowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overfow allo wing the programmer to use the struct ure more easily . however , when the stack is full, a call subroutine instruction can still be execu ted which will result in a stack overfow . precautions should be taken to avoid such cases which might cause unpredictable program branching. if the stack is overfow, the frst program counter save in the stack will be lost. sta?k pointe? sta?k level ? sta?k level 1 sta?k level ? : : : sta?k level ? p?og?am ?emo?y p?og?am counte? bottom of sta?k top of sta?k a?it?meti? and logi? unit C alu the arith metic-logic unit or alu is a critical area of the microcontrol ler that carries out arithmetic and logic operations of the instructi on set. connected to the main micro controller data bus, the alu receives related ins truction codes and performs the required arithmetic or logical operations after which the result will be placed in the specifed register . as these alu calculation or operations may result in carry , borrow or other status changes, the status register will be correspondingly updated to refect these changes. the alu supports the following functions: ? arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa, ladd, laddm, ladc, ladcm, lsub, lsubm, lsbc, lsbcm, ldaa ? logic operations: and, or, xor, andm, orm, xorm, cpl, cpla, land, landm, lor, lorm, lxor, lxorm, lcpl, lcpla ? rotation rra, rr, rrca, rrc, rla, rl, rlca, rlc, lrr, lrra, lrrca, lrrc, lrla, lrl, lrlca, lrlc ? increment and decrement inca, inc, deca, dec, linca, linc, ldeca, ldec ? branch decision, jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti, lsnz, lsz, lsza, lsiz, lsiz, lsdz, lsdza
rev. 1.00 18 ?a??? 0?? ?01? rev. 1.00 19 ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu flash prora meor the program memory is the locatio n where the user code or program is stored. for this device the program memory is flash type, which means it can be programmed and re-programmed a lar ge number o f t imes, a llowing t he u ser t he c onvenience o f c ode m odification o n t he sa me d evice. by using the appropriate programming tools, this flash device of fers users the flexibility to conveniently debug and develop their applications while also of fering a means of feld programming and updating. the progra m me mory ha s a c apacity of 2k16 bi ts. t he progra m me mory i s a ddressed by t he program counter and also contains data, table information and interrupt entries. t able data, which can be setup in any location within the program memory , is addressed by a separate table pointer register. reset inte??upt ve?to?s 1? bits 0000h 0004h 00?ch 07ffh p?og?am ?emo?y st?u?tu?e spe?ial ve?to?s within the program memory , certai n locations are reserved for the reset and interrupts. the location 000h is reserved for use by the device reset for program initialisation. after a device reset is initiated, the program will jump to this location and begin execution. any location within the program memory can be defned as a look-up table where programmers can store fxed data. t o use the look-up table, the table pointer must frst be setup by placing the address of the look up data to be retrieved in the table pointer register , tblp and tbhp . these registers defne the total address of the look-up table. after setting up the table pointer, the table data can be retrieved from the program memory using the corresponding table read instruction such as t abrd [m] or t abrdl [m] respectively when the memory [m] is located in sector 0. if the memory [m] is located in other sectors, the data can be retrieved from the program memory using the corresponding extended table read instruction such as ltabrd [m] or l tabrdl [m] respectively . when the instruction is executed, the lower order table byte from the program memory will be transferred to the user defned data memory register [m] as specifed in the instruction. the higher order table data byte from the program memory will be transferred to the tblh special register.
rev. 1.00 ? 0 ? a ??? 0 ?? ? 01 ? rev. 1.00 ?1 ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu the accompanying diagram illustrates the addressing data fow of the look-up table. last page o? tbhp registe? tblp registe? p?og?am ?emo?y registe? tblh use? sele?ted registe? add?ess data 1? bits hig? byte low byte table p?og?am example the following example shows how the table pointer and table data is defned and retrieved from the microcontroller . this example us es raw table data located in the p rogram m emory w hich is stored there using the org statement. the value at this org statement is 0700h which refers to the start address of the last page within the 2k program memory of the microcontroller . the table pointer low byte register is setup here to have an initial value of 06h. this will ensure that the frst data read from the data table will be at the program memory address 0706h or 6 locations after the start of the last page. note that the value for the table pointer is referenced to the frst address specifed by tblp and tbhp if the t abrd [m] or l tabrd [m] instruction is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the tabrd [m] or ltabrd [m] instruction is executed. because the tblh register is a read/write register and can be restored, care should be taken to ensure its protection if both the main routine and interrupt s ervice routine us e table read instructions. if using the table read instructions, the interrupt service routines may change the value of the tblh and subsequently cause errors if used again by the main routine. as a rule it is recommended that simultaneous use of the table read instructions should be avoided. however , in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation. tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialise low table pointer - note that this address is referenced mov tblp,a ; to the last page or the page that tbhp pointed mov a,07h ; initialise high table pointer mov tbhp,a : : tabrd tempreg1 ; transfers value in table referenced by table pointer data at program ; memory address 0706h transferred to tempreg1 and tblh dec tblp ; reduce value of table pointer by one tabrd tempreg2 ; transfers value in table referenced by table pointer ; data at program memory address 0705h transferred to ; tempreg2 and tblh in this example the data 1ah is ; transferred to tempreg1 and data 0fh to register tempreg2 : : org 0700h ; sets initial address of program memory dc 00ah, 00bh, 00ch, 00dh, 00eh, 00fh, 01ah, 01bh : :
rev. 1.00 ?0 ?a??? 0?? ?01? rev. 1.00 ? 1 ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu n cirit prorain cp the provision of flash type program memory provides the user with a means of convenient and easy upgrades a nd m odifcations t o t heir p rograms o n t he sa me d evice. as a n a dditional c onvenience, holtek has provided a means of programming the microcontroller in-circuit using a 4-pin interface. this provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller , and then programming or upgrading the program at a later stage. this enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device. the holtek flash mcu to w riter programming pin correspondence table is as follows: icpda pa0 p ? og ? amming se ? ial data/add ? ess icpck pa ? p ? og ? amming clo ? k vdd vdd powe ? supply vss vss g ? ound the program memory and eeprom data memory can be programme d serially in-circuit using this 4-wire interface. data is downloaded and uploaded serially on a single pin with an additional line for the clock. t wo additional lines are required for the power supply . the technical details regarding the in-cir cuit programming of the device are beyond the scope of this document and will be supplied in supplementary literature. during the programming process, taking control of the icpda and icpck pins for data and clock programming purposes. the user must there take care to ensure that no other outputs are connected to these two pins. * * w?ite?_vdd icpda icpck w?ite?_vss to ot?e? ci??uit vdd pa0 pa? vss w?ite? conne?to? signals ?cu p?og?amming pins note: * may be resistor or capacito r. the resistance of * must be great er than 1k or the capacitance of * must be less than 1nf.
rev. 1.00 ?? ? a ??? 0 ?? ? 01 ? rev. 1.00 ?? ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu n chi e ort c there is an ev chip named ht45v3630 which is used to emulate the HT45F3630 device. the ev chip device also provides an on-chip debug function to debug the real mcu device during the development process. the ev chip and the real mcu device are almost functionally compatible except for on-chip debug function. users can use the ev chip device to emulate the real chip device behavior by connecting the ocdsda and ocdsck pins to the holtek ht -ide development tools. the ocdsda pin is the ocds data/address input/output pin while the ocdsck pin is the ocds clock input pin. when users use the ev chip for debugging, other functions which are shared with the ocdsda and ocdsck pins in the device will have no ef fect in the ev chip. however , the two ocds pins which are pin-shared with the icp programming pins are still used as the flash memory programming pins for icp . for more detailed ocds information, refer to the corresponding document named holtek e-link for 8-bit mcu ocds users guide. ocdsda ocdsda on-c ? ip debug suppo ? t data/add ? ess input/output ocdsck ocdsck on-c ? ip debug suppo ? t clo ? k input vdd vdd powe ? supply vss vss g ? ound data ?emo?y the data memory is a volatile area of 8-bit wide ram internal memory and is the location where temporary information is stored. categorized into two types, the first of these is an area of ram where special function registers are located. these registers have fxed locations and are necessary for correct operation of the device. many of these registers can be read from and written to directly under program control, however , some remain protected from user manipulation. the second area of data memory is reserved for general purpose use. all locations within this area are read and write accessible under program control. the da ta me mory i s subdi vided i nto se veral se ctors, a ll of wh ich a re i mplemented i n 8-b it wi de ram. each of the d ata m emory s ector is categorized into tw o types , the s pecial p urpose d ata memory and the general purpose data memory . the special purpose data memory registers are accessible in sector 0, with the exception of the eec register at address 40h, which is only accessible in sector 1. switching between the dif ferent data memory sectors is achieved by setting the memory pointers to the correct value. the start address of the data memory is the address 00h. 0: 00h~7fh 1: 40h ? 48 0: 80h~bfh 00h 7fh 80h spe?ial pu?pose data ?emo?y gene?al pu?pose data ?emo?y se?to? 0 eec at 40h in se?to? 1 bfh data ?emo?y st?u?tu?e
rev. 1.00 ?? ?a??? 0?? ?01? rev. 1.00 ?? ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu eneral prose ata meor there are 64 bytes of general purpose data memory which are arranged in 80h~bfh of sector 0. all microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later . it is this area of ram memory that is known as general purpose data memory. this area of data memory is fully accessible by the user programing for both reading and writing operations. by using the bit operation instructions individual bits can be set or reset under program control giving the user a large range of fexibility for bit manipulation in the data memory. this area of data memory is where registers, necessary for the correct operation of the microcontroller, are stored. most of the registers are both readable and writeable but some are protected and are readable only , the details of which are located under the relevant special function register section. note that for locat ions that are unused, any read instruction to these addresses will return the value 00h. 00h iar 0 01h ?p 0 0?h iar 1 0?h ?p 1l 04h 05h acc 0?h pcl 07h tblp 08h tblh 09h tbhp 0 ah status 0 bh 0 ch 0 dh 0 eh 0 fh 10h pb 11h 1?h 19h pa 18h pac 1 bh 1 ah 1 dh 1 ch 1 fh pbpu ocpc 0 1?h 14h 15h 1?h 17h sadc 0 ?0h ?1h ??h ?8h ??h ?4h ?5h ??h ?7h 1 eh hircc sadol scc ?p 1h iar ? ?p ?l ?p ?h rstfc pawu pbc papu pas 0 pas 1 sadoh sadc 1 sledc integ lvrc lvdc ocpc 1 ocpda ocpocal pbs 0 ocpccal se?to? 0 se?to? 1 se?to? 0 se?to? 1 intc 0 iicd iica ?9h ? bh ? ah ? dh ? ch ? fh ? eh intc 1 iicc 1 iictoc iicc 0 eea pt? 1c0 pt? 1c1 pt? 1 dl pt? 1 dh pt? 1 al pt? 1 ah eed pt? 1 rpl pt? 1 rph hvoc hvopc eec pt? 0c0 pt? 0c1 pt? 0 al pt? 0 ah pt? 0 dl pt? 0 rpl pt? 0 rph pt? 0 dh intc ? ?fi 0 ?fi 1 pscr tb 0c tb 1c wdtc 40h 41h 4?h 4?h 44h 45h 4?h 47h 48h 49h 4 ah 4 bh 4 ch 4 dh 7 fh ?0h ?1h ??h ?8h ? ch ??h ?4h ?5h ??h ?7h ? bh ?9h ? ah ? dh ? fh ? eh : unused ? ?ead as 00h spe?ial pu?pose data ?emo?y
rev. 1.00 ? 4 ? a ??? 0 ?? ? 01 ? rev. 1.00 ?5 ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu eial fntion eister esrition most of the special function register details will be described in the relevant functional section, however several registers require a separate description in this section. the indirect addressing registers, iar0, iar1 and iar2, although having their locations in normal ram r egister sp ace, d o n ot a ctually p hysically e xist a s n ormal r egisters. t he m ethod o f i ndirect addressing for ram da ta m anipulation use s t hese indi rect addre ssing re gisters a nd me mory pointers, i n c ontrast t o di rect m emory a ddressing, where t he a ctual m emory a ddress i s spe cifed. actions on t he iar0, iar1 a nd iar2 re gisters wi ll re sult i n no a ctual re ad or writ e ope ration t o these registers but rather to the memory location specifed by their corresponding memory pointers, mp0, mp1l/mp1h or mp2l/mp2h. acting as a pair , iar0 and mp0 can together access data only from sector 0 while the iar1 register together with the mp1l/mp1h register pair and iar2 register together with the mp2l/mp2h register pair can access data from any data memory sector . as the indirec t addressing re gisters are not physi cally i mplemented, rea ding t he indirec t addressing registers will return a result of 00h and writing to the registers will result in no operation. five memory pointers, known as mp0, mp1l, mp1h, mp2l, mp2h, are provided. these memory pointers are physically implemente d in the data memory and can be manipulated in the same way as n ormal r egisters p roviding a c onvenient wa y wi th wh ich t o a ddress a nd t rack d ata. w hen a ny operation to the relevant indirect addressing registers is carried out, the actual address that the microcontroller is directed to is the address specifed by the related memory pointer . mp0, together with indirect addressing register , iar0, are used to access data from sector 0, while mp1l/mp1h together with iar1 and mp2l/mp2h together with iar2 are used to access data from all sectors according t o t he c orresponding mp1h or mp2h regi ster. di rect addre ssing ca n be use d i n a ll sectors using the corresponding instruction which can address all available data memory space. the following example shows how to clear a section of four data memory locations already defned as locations adres1 to adres4. data .section data adres1 d b ? adres2 d b ? adres3 d b ? adres4 d b ? block d b ? code .section at 0 code org 00h start: m ov a, 04h ; setup size of block m ov block, a mov a , o ffset ad res1 ; a ccumulator l oaded w ith f rst r am ad dress mov m p0, a ; s etup m emory po inter wi th f rst r am a ddress loop: clr i ar0 ; c lear t he d ata a t ad dress d efned b y m p0 i nc mp0 ; increment memory pointer s dz block ; check if last memory location has been cleared jm p loop continue:
rev. 1.00 ?4 ?a??? 0?? ?01? rev. 1.00 ? 5 ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu niret ressin prora ale data .section data adres1 d b ? adres2 d b ? adres3 d b ? adres4 d b ? block d b ? code .section at 0 code org 00h start: m ov a, 04h ; setup size of block m ov block, a m ov a, 01h ; setup the memory sector m ov mp1h, a mov a , o ffset ad res1 ; a ccumulator l oaded w ith f rst r am ad dress mov m p1l, a ; s etup m emory po inter wi th f rst r am a ddress loop: clr i ar1 ; c lear t he d ata a t a ddress d efned b y m p1l inc m p1l ; i ncrement m emory po inter m p1l s dz block ; check if last memory location has been cleared jm p loop continue: the important point to note here is that in the example shown above, no reference is made to specifc data memory addresses. data .section data temp db ? code .section at 0 code org 00h start: l mov a, [m] ; move [m] data to acc l sub a, [m+1] ; compare [m] and [m+1] data s nz c ; [m]>[m+1]? j mp continue ; no l mov a, [m] ; yes, exchange [m] and [m+1] data m ov temp, a l mov a, [m+1] l mov [m], a m ov a, temp l mov [m+1], a continue: note: here m is a data memory address located in any data memory sectors. for example, m=1f0h, it indicates address 0f0h in sector 1. the a ccumulator is central to the operation of any microcontroller and is clos ely related w ith operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. w ithout the accumulator it would be necessary to write the result of each c alculation or l ogical ope ration suc h a s a ddition, subt raction, shi ft, e tc., t o t he da ta me mory resulting i n highe r program ming and t iming overheads. da ta t ransfer operat ions usual ly i nvolve the t emporary st orage func tion of t he ac cumulator; for e xample, wh en t ransferring da ta be tween one user -defined register and another , it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted.
rev. 1.00 ?? ? a ??? 0 ?? ? 01 ? rev. 1.00 ?7 ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu prora conter ow eister pc to provide additional program control functions, the low byte of the program counter is made accessible to programmers by locating it within the special purpose area of the data memory . by manipulating this register , direct jumps to other program locations are easily implemented. loading a value directly into this pcl register will cause a jump to the specifed program memory location, however, as the register is only 8-bit wide, only jumps within the current program memory page are permitted. when such operations are used, note that a dummy cycle will be inserted. these three special function registers are used to cont rol operation of the look-up table which is stored i n t he progra m me mory. t blp a nd t bhp a re t he t able poi nters a nd i ndicate t he l ocation where the table data is located. their value must be setup before any table read commands are executed. their value can be changed, for example using the inc or dec instructions, allowing for easy table data pointing and reading. tblh is the location where the high order byte of the table data is stored afte r a table read data instruction has been executed. note that the lower order table data byte is transferred to a user defned location. this 8-bit register contains the sc fag, cz fag, zero fag (z), carry fag (c), auxiliary carry fag (ac), overfow fag (ov), power down fag (pdf), and watchdog time-out fag (t o). these arithmetic/ logical o peration a nd sy stem m anagement fa gs a re u sed t o r ecord t he st atus a nd o peration o f t he microcontroller. with the exceptio n of the t o and pdf fags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the t o or pdf fag. in addition, operations related to the status register may give dif ferent results due to the dif ferent instruction operati ons. the t o fag can be af fected only by a system power -up, a wdt time-out or by executing the clr wdt or hal t instruction. the pdf fag is af fected only by executing the halt or clr wdt instruction or during a system power-up. the z, ov, ac, c, sc and cz fags generally refect the status of the latest operations. ? c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also af fected by a rotate through carry instruction. ? ac is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. ? z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. ? ov is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. ? pdf is cleared by a system power -up or executing the clr wdt instruction. pdf is set by executing the halt instruction. ? to is cle ared by a system power -up or executing the clr wdt or hal t instruction. to is set by a wdt time-out. ? cz is the operational result of dif ferent flags for dif ferent instructions. refer to register defnitions for more details. ? sc is the result of the xor operation which is performed by the ov fag and the msb of the current instruction operation result.
rev. 1.00 ?? ?a??? 0?? ?01? rev. 1.00 ? 7 ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu in additio n, on entering an interrup t sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically . if the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. name sc cz to pdf ov z ac c r/w r r r r r/w r/w r/w r/w por x x 0 0 x x x x x unknown bit 7 sc : xor operation result - performed by the ov fag and the msb of the instruction operation result. bit 6 cz : operational result of different fags for different instructions. for sub/subm/lsub/lsubm instructions, the cz fag is equal to the z fag. for s bc/ s bcm/ ls bc/ ls bcm ins tructions, the cz f ag is the a nd operation result which is performed by the previous operation cz fag and current operation zero fag. for other instructions, the cz fag will not be affected. bit 5 to : w atchdog t ime-out fag 0: after power up or executing the clr wdt or halt instruction 1: a watchdog time-out occurred. bit 4 pdf : power down fag 0: after power up or executing the clr wdt instruction 1: by executing the halt instruction bit 3 ov : overfow fag 0: no overfow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. bit 2 z : zero fag 0: the result of an arithmetic or logical operation is not zero 1: the result of an arithmetic or logical operation is zero bit 1 ac : auxiliary fag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction bit 0 c : carry fag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation c is also affected by a rotate through carry instruction.
rev. 1.00 ? 8 ? a ??? 0 ?? ? 01 ? rev. 1.00 ?9 ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu pm ata meor this device contains an area of internal eeprom data memory . eeprom, which stands for electrically e rasable progra mmable re ad onl y me mory, i s by i ts na ture a non-vol atile form of re-programmable memory , with data retention even when its power supply is removed. by incorporating this kind of data memory , a w hole new hos t of application pos sibilities are made available to the designer . the avail ability of eeprom storage allows information such as product identification numbers, calibration values, specific user data, system setup data or other product information to be stored directly within the product microcontroller . the process of reading and writing data to the eeprom memory has been reduced to a very trivial affair. the eeprom data memory capacity is 328 bits for the device. unlike the program memory and ram data memory , the eeprom data memory is not directly mapped into memory space and is therefore not directly addressable in the same way as the other types of memory . read and w rite operations to the eeprom are carried out in single byte operations using an address and a data register in sector 0 and a single control register in sector 1. three registers control the overall operation of the internal eeprom data memory . these are the address register , eea, the data register , eed and a single control register , eec. as both the eea and eed registers are located in sector 0, they can be directly accessed in the same was as any other special function register . the eec register however , being located in sector 1, can be read from or written to indirectly using the mp1l/mp1h or mp2l/mp2h memory pointer and indirect addressing register , iar1/iar2. because the eec control register is located at address 40h in sector 1, the mp1l or mp2l memory pointer must frst be set to the value 40h and the mp1h or mp2h memory pointer high byte set to the value, 01h, before any operations on the eec register are executed. eea eea4 eea ? eea ? eea1 eea0 eed eed7 eed ? eed5 eed4 eed ? eed ? eed1 eed0 eec wren wr rden rd eepro? registe? list eea registe? bit 7 ? 5 4 ? ? 1 0 name eea4 eea ? eea ? eea1 eea0 r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7~5 unimplemented, read as 0 bit 4~0 eea4~eea0 : data eeprom address data eeprom address bit 4 ~ bit 0
rev. 1.00 ?8 ?a??? 0?? ?01? rev. 1.00 ? 9 ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu eister bit 6 5 4 3 0 name eed7 eed ? eed5 eed4 eed ? eed ? eed1 eed0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 eed7~eed0 : data eeprom data data eeprom data bit 7 ~ bit 0 name wren wr rden rd r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~4 unimplemented, read as 0 bit 3 wren : data eeprom w rite enable 0: disable 1: enable this is the d ata eep rom w rite enable bit w hich mus t be s et high before d ata eeprom write operations are carried out. clearing this bit to zero will inhibit data eeprom write operations. bit 2 wr : eeprom w rite control 0: w rite cycle has fnished 1: activate a write cycle this i s t he da ta e eprom w rite c ontrol b it a nd wh en se t h igh b y t he a pplication program will activ ate a write cycle. this bit will be automatically reset to zero by the hardware after the write cycle has fnished. setting this bit high will have no ef fect if the wren has not frst been set high. bit 1 rden : data eeprom read enable 0: disable 1: enable this is the data eeprom read enable bit which must be set high before data eeprom read operations are carried out. clearing this bit to zero w ill inhibit d ata eeprom read operations. bit 0 rd : eeprom read control 0: read cycle has fnished 1: activate a read cycle this is the data eeprom read control bit and when set high by the applic ation program will activ ate a read cycle. this bit will be automatically reset to zero by the hardware after the read cycle has fnished. setting this bit high will have no ef fect if the rden has not frst been set high. note: the wren, wr, rden and rd cannot be set high at the same time in one instruction. the wr and rd cannot be set high at the same time.
rev. 1.00 ? 0 ? a ??? 0 ?? ? 01 ? rev. 1.00 ?1 ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu eain ata ro the pm to read data from the eep rom, the read enable bit, rden , in the eec register must frs t be set high to enable the read function. the eeprom address of the data to be read must then be placed in the eea register . if the rd bit in the eec register is now set high, a read cycle will be initiated. setting the rd bit high will not initiate a read operation if the rden bit has not been set. when the read cycle term inates, the rd bit will be automatically cleared to zero, after which the data can be read from the eed register . the data will remain in the eed register until another read or write operation i s e xecuted. t he a pplication pr ogram c an po ll t he rd bi t t o de termine whe n t he da ta i s valid for reading. the eeprom address of the data to be written must frst be placed in the eea register and the data placed in the eed register . t o write data to the eeprom, the write enable bit, wren, in the eec register must frst be set high to enable the write function. after this, the wr bit in the eec register must be immediately set high to initiate a write cycle. these two instructions must be executed consecutively. the global interrupt bit emi should als o frs t be cleared before implementing any write operat ions, and then set agai n aft er the write cyc le has start ed. note that setting the wr bi t high will not initiate a write cycle if the wren bit has not been set. as the eeprom write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the eeprom. detecting when the write cycle has fnished can be implemented either by polling the wr bit in the eec register or by using the eeprom interrupt. when the write cycle terminates, the wr bit will be automatically cleared to zero by the microcontroller , informing the user that the data has been written to the eeprom. the application program can therefore poll the wr bit to determine when the write cycle has ended. protection against inadvertent write operation is provided in several ways. after the device is powered-on t he w rite e nable b it i n t he c ontrol r egister wi ll b e c leared p reventing a ny wr ite operations. also at power -on the memory pointer high byte register , mp1h or mp2h, will be reset to zero, which means that data memory sector 0 will be selected. as the eeprom control register is located in sector 1, this adds a further measure of protection against spurious write operations. during normal program operati on, ensuring that the w rite enable bit in the cont rol re gister is cleared will safeguard against incorrect write operations. the eeprom write interrupt is generated when an eeprom write cycle has ended. the eeprom interrupt must first be enabled by setting the dee bit in the relevant interrupt register . when an eeprom write cycle ends, the def request fag will be set. if the global, eeprom interrupts are enabled and the stack is not full, a jump to the associated eeprom interrupt vector will take place. when t he i nterrupt i s se rviced, t he e eprom i nterrupt r equest f lag, de f, wi ll b e a utomatically reset and the emi bit will be autom atically cleared to disable other interrupts. more details can be obtained in the interrupt section.
rev. 1.00 ?0 ?a??? 0?? ?01? rev. 1.00 ? 1 ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu prorain consierations care must be taken that data is not inadvertently written to the eeprom. protection can be enhanced by ensuring that the w rite enable bit is normally cleared to zero when not writing. also the memory pointer high byte register , mp1h or mp2h, could be normally cleared to zero as this would inhibit access to sector 1 where the eeprom control register exist. although certainly not necessary, consideration might be given in the application program to the checking of the validity of new write data by a simple read back process. when writing data the wr bit must be set high immediately after the wren bit has been set high, to ensure the write cycle executes correctly . the global interrupt bit emi should also be cleared before a write cycle is executed and then re-enabled after the write cycle starts. note that the device should not enter the id le or sleep mode until the eeprom read or write operation is totally complete. otherwise, the eeprom read or write operation will fail. mov a, ee prom_adres ; u ser d efned ad dress mov eea, a mov a, 0 40h ; se tup m emory p ointer m p1l mov mp1l, a ; mp1 p oints t o e ec r egister mov a, 0 1h ; se tup m emory p ointer m p1h mov mp1h, a set iar1.1 ; s et r den b it, e nable r ead o perations set iar1.0 ; s tart r ead c ycle - s et r d b it back: sz iar1.0 ; c heck f or re ad c ycle e nd jmp back clr iar1 ; d isable ee prom re ad/write clr mp1h mov a, ee d ; m ove re ad d ata t o re gister mov read_data, a mov a, ee prom_adres ; u ser d efned ad dress mov eea, a mov a, e eprom_data ; u ser d efned da ta mov eed, a mov a, 0 40h ; se tup m emory p ointer m p1l mov mp1l, a ; mp1 p oints t o e ec r egister mov a, 0 1h ; se tup m emory p ointer m p1h mov mp1h, a clr emi set iar1.3 ; s et w ren b it, e nable w rite o perations set iar1.2 ; s tart w rite c ycle - s et w r b it e xecuted i mmediately ; a fter s et w ren b it set emi back: sz iar1.2 ; c heck f or wr ite c ycle e nd jmp back clr iar1 ; d isable ee prom re ad/write clr mp1h
rev. 1.00 ?? ? a ??? 0 ?? ? 01 ? rev. 1.00 ?? ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu sillators various oscillator options of fer the user a wide range of functions according to their various application requirements. the flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. oscillator selections and operation are selected through registers. in additio n to being the source of the main system clock the oscillators also provide clock sources for the w atchdog t imer and t ime base interrupts. fully integrated inte rnal oscillators, requiring no external components, are provided to form a wide range of both fast and slow system oscillators. the h igher f requency o scillators p rovide h igher p erformance b ut c arry wi th i t t he d isadvantage o f higher power requirements, while the opposite is of course true for the lower frequency oscillators. with the capabilit y of dynamically switching between fast and slow system clock, the device has the fexibility to optim ize the performance/power ratio, a feature especially important in power sensitive portable applications. inte ? nal hig ? speed rc hirc 8 ? hz inte ? nal low speed rc lirc ?? khz os?illato? types system clock confgurations there are two methods of generating the system clock, one high speed oscillator and one low speed oscillator. the high speed oscillator is the internal 8mhz rc oscillato r. the low speed oscillator is the intern al 32khz rc oscillator . selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the cks2~cks0 bits in the scc register and as the system clock can be dynamically selected. the frequency of the slow speed or high speed system clock is also determined using cks2~cks0 bits in the scc register. note that two oscillator selections m ust be made namely one high speed and one low speed system oscillators. it is not possible to choose a no-oscillator selection for either the high or low speed oscillator. p?es?ale? f h hig? speed os?illato? low speed os?illato? f h /? f h /1? f h /?4 f h /8 f h /4 f h /?? cks?~cks0 f sys f sub f sub f lirc f lirc sleep idle0 idle? sleep hirc hircen lirc system clock confgurations
rev. 1.00 ?? ?a??? 0?? ?01? rev. 1.00 ?? ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu nternal c sillator hc the internal rc oscillator is a fully integrated system oscillator requiring no external components. the i nternal r c o scillator h as a f ixed f requency o f 8 mhz. de vice t rimming d uring t he manufacturing process and the inclusion of internal frequency compensati on circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. it requires no external pins for its operation. the i nternal 3 2khz sy stem osc illator i s t he l ow f requency o scillator. i t i s a f ully i ntegrated rc osc illator wi th a t ypical fre quency of 32khz a t 5v , re quiring no e xternal c omponents for i ts implementation. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. present day appl ications require that their mi crocontrollers have high performance but often sti ll demand that they consume as little power as possible, conficting requirements that are especially true i n ba ttery powe red por table a pplications. t he fa st c locks re quired for hi gh pe rformance wi ll by t heir na ture i ncrease c urrent c onsumption a nd of c ourse vi ce-versa, l ower spe ed c locks re duce current consumption. as holtek has provided this device with both high and low speed clock sources and the means to switch between them dynamically , the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. the devic e has many dif ferent clock sources for both the cpu and peripheral function operation. by providing the user with a wide range of clock options using register programming, a clock system can be confgured to obtain maximum application performance. the m ain sy stem c lock, c an c ome f rom e ither a h igh f requency f h o r l ow f requency f sub so urce, and is selected using the cks2~cks0 bits in the s cc register . the high speed system clock can be sourced from the hirc oscillator . the low speed system clock source can be sourced from the lirc oscillator . the other choice, which is a divided version of the high speed system oscillator has a range of f h /2~f h /64.
rev. 1.00 ? 4 ? a ??? 0 ?? ? 01 ? rev. 1.00 ?5 ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu p?es?ale? f h hig? speed os?illato? low speed os?illato? f h /? f h /1? f h /?4 f h /8 f h /4 f h /?? cks?~cks0 f sys f sub f sub f sys /4 f psc clksel[1:0] wdt f lirc f lirc time bases p?es?ale? f sub f sys tb0[?:0] tb1[?:0] lvr f lirc sleep idle0 idle? sleep hirc hircen lirc device clock confgurations note: when the system clock source f is switched to f from f h , the high speed oscillator can be stopped to conserve the power or continue to oscillate to provide the clock source, f h ~ f h /64, for peripheral circuit to use, which is determined by confguring the corresponding high speed oscillator enable control bit. system operation modes there are six dif ferent modes of operation for the microcontroller , each one with its ow n special characteristics and which can be chosen according to the specific performance and power requirements of the appl ication. there are two modes all owing normal operati on of the microcontroller, the normal mode and slow mode. the remaining four modes, the sleep , dle0, idle1 and idle2 mode are used when the microcontroller cpu is switched of f to conserve power. operation mode cpu register setting f sys f h f sub f lirc fhiden fsiden cks2~cks0 nor ? al on x x 000~110 f h ~ f h / ? 4 on on on slow on x x 111 f sub on/off (1) on on idle0 off 0 1 000~110 off off on on 111 on idle1 off 1 1 xxx on on on on idle ? off 1 0 000~110 on on off on 111 off sleep off 0 0 xxx off off off on/off ( ? ) x: dont ? a ? e note: 1. the f h clock will be switched on or of f by confguring the corresponding oscillator enable bit in the slow mode. 2. the f lirc clock can be switched on or of f which is controlled by the wdt function being enabled or disabled in the sleep mode .
rev. 1.00 ?4 ?a??? 0?? ?01? rev. 1.00 ? 5 ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu m moe as the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by the high speed oscillator . this mode operates allo wing the microco ntroller to operate normally with a clock source will come from the h igh sp eed o scillator hi rc. t he h igh sp eed o scillator wi ll h owever fr st b e d ivided b y a r atio ranging from 1 to 64, the actual ratio being s elected by the ck s2~cks0 bits in the s cc regis ter. although a high speed oscillator is used, running the microcontroller at a divided clock ratio reduces the operating current. this is also a mode where the microcontroller operates normally although now with a slower speed clock s ource. the clock s ource us ed w ill be from f sub . the f sub clock is derived from the lirc osc illator. running t he m icrocontroller i n t his m ode a llows i t t o run wi th m uch l ower operating currents. in the slow mode, the f h clock will be switched on or of f by confguring the corresponding oscillator enable bit hircen. the sleep mode is entered when an hal t instruction is executed and when the fhiden and fsiden bit are low . in the sleep mode the cp u will be stopped . however the f lirc clock can still c ontinue t o o perate if t he w dt f unction i s enabled , t he f lirc c lock wi ll b e st opped t oo, i f t he watchdog t imer function is disabled. the idle0 mode is entered when an hal t instruction is executed and when the fhiden bit in the s cc regis ter is low and the f siden bit in the s cc regis ter is high. in the id le0 m ode the cpu wi ll be swi tched of f but t he l ow spe ed osc illator wi ll be t urned on t o dri ve som e pe ripheral functions. the idle1 mode is entered when an hal t instruction is executed and when the fhiden bit in the scc register is high and the fsiden bit in the scc register is high. in the idle1 mode the cpu will be switched of f but both the high and low speed oscillators will be turned on to provide a clock source to keep some peripheral functions operational. the idle2 mode is entered when an hal t instruction is executed and when the fhiden bit in the scc register is high and the fsiden bit in the scc register is low . in the idle2 mode the cpu will be switched of f but the high speed oscillator will be turned on to provide a clock source to keep some peripheral functions operational.
rev. 1.00 ?? ? a ??? 0 ?? ? 01 ? rev. 1.00 ?7 ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu control eister the re gisters, scc a nd hircc, a re use d t o c ontrol t he syst em c lock a nd t he c orresponding oscillator confgurations. name cks ? cks1 cks0 fhiden fsiden r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7~5 cks2~cks0 : system clock selection 000: f h 001: f h /2 010: f h /4 011: f h / 100: f h /16 101: f h /32 110: f h /4 111: f these three bits are used to select which clock is used as the system clock source. in addition to the system clock source directly derived from f h or f , a divided version of the high speed system oscillator can also be chosen as the system clock source. bit 4~2 unimplemented, read as 0 bit 1 fhiden : high frequency oscillator control when cpu is switched off 0: disable 1: enable this bit is used to control whether the high speed oscillator is activated or stopped when the cpu is switched off by executing an halt instruction. bit 0 fsiden : low frequency oscillator control when cpu is switched off 0: disable 1: enable this bi t i s use d t o cont rol whe ther t he l ow spe ed osc illator i s ac tivated or st opped when the cpu is sw itched of f by executing an h alt instruction. the lirc oscillator is controlled by this bit together with the wdt function enable control when the lirc is selected to be the low speed oscillator clock source or the wdt function is enabled respectively . if this bit is cleared to 0 but the wdt function is enabled, the lirc oscillator will also be enabled. name hircf hircen r/w r/w r/w por 0 1 bit 7~2 unimplemented, read as 0 bit 1 hircf : hirc oscillator stable fag 0: hirc unstable 1: hirc stable this bit is used to indi cate whe ther the hirc oscilla tor is stable or not. when the hircen bit is s et to 1 to enable the h irc os cillator, the h ircf bit w ill firs t be cleared to 0 and then set to 1 after the hirc oscillator is stable. bit 0 hircen : hirc oscillator enable control 0: disable 1: enable
rev. 1.00 ?? ?a??? 0?? ?01? rev. 1.00 ? 7 ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu eratin moe within the devi ce c an swi tch bet ween opera ting m odes dynam ically a llowing t he use r t o se lect t he best performance/power ratio for the pres ent task in hand. in this w ay microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. in simple terms, mode switching between the normal mode and slow mode is executed using the cks2~cks0 bits in the scc register while mode switching from the normal/slow modes to the sleep/idle modes is executed via the hal t instructio n. when a hal t instruction is executed, whether the device enters the idle mode or the sleep mode is determined by the condition of the fhiden and fsiden bits in the scc register. f sys =f h ~f h /?4 f h on cpu ?un f sys on f sub on slow f sys =f sub f sub on cpu ?un f sys on f h on/off idle0 halt inst?u?tion exe?uted cpu stop fhiden=0 fsiden=1 f h off f sub on idle1 halt inst?u?tion exe?uted cpu stop fhiden=1 fsiden=1 f h on f sub on idle? halt inst?u?tion exe?uted cpu stop fhiden=1 fsiden=0 f h on f sub off sleep halt inst?u?tion exe?uted cpu stop fhiden=0 fsiden=0 f h off f sub off
rev. 1.00 ? 8 ? a ??? 0 ?? ? 01 ? rev. 1.00 ?9 ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu m moe to moe within when r unning i n t he nor mal mo de, wh ich u ses t he h igh sp eed sy stem o scillator, a nd t herefore consumes m ore powe r, t he syste m c lock c an swit ch t o run i n t he sl ow mode by se t t he cks2~cks0 b its t o 111 i n t he sc c r egister. t his wi ll t hen u se t he l ow sp eed sy stem o scillator which wi ll c onsume l ess po wer. use rs m ay de cide t o do t his fo r c ertain op erations whi ch do no t require high performance and can subsequently reduce power consumption. the slow mode is sourced from the lirc oscillator and therefore requires this oscillator to be stable before full mode switching occurs. cks?~cks0 = 111 sleep ?ode fhiden=0? fsiden=0 halt inst?u?tion is exe?uted idle0 ?ode fhiden=0? fsiden=1 halt inst?u?tion is exe?uted idle1 ?ode fhiden=1? fsiden=1 halt inst?u?tion is exe?uted idle? ?ode fhiden=1? fsiden=0 halt inst?u?tion is exe?uted
rev. 1.00 ?8 ?a??? 0?? ?01? rev. 1.00 ? 9 ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu moe to m moe within in slow mode the system clock is derived from f sub . when system clock is switch ed back to the normal mode from f sub , the cks2~cks 0 bits should be set to 000 ~11 0 and then the system clock will respectively be switch ed to f h ~ f h /64. h owever, if f h i s not use d i n sl ow m ode a nd t hus swi tched of f , i t wi ll t ake som e t ime t o re - oscillat e and stabili se when switching to the normal mode from the slow mode . this is monitored using the hircf bit in the hircc register . the time duration required for the high speed system oscillator stabilization is specifed in the a.c. characteristics. cks?~cks0 = 000~110 sleep ?ode fhiden=0? fsiden=0 halt inst?u?tion is exe?uted idle0 ?ode fhiden=0? fsiden=1 halt inst?u?tion is exe?uted idle1 ?ode fhiden=1? fsiden=1 halt inst?u?tion is exe?uted idle? ?ode fhiden=1? fsiden=0 halt inst?u?tion is exe?uted ente?ing t?e sleep ?ode there is only one way for the device to enter the sleep mode and that is to execute the hal t instruction in the application program with both the fhiden and fsiden bit in scc register equal to 0. in this mode all the clocks and functions wi ll be switched of f except the wdt function. when this instruction is executed under the conditions described above, the following will occur: ? the system clock will be stopped and the application program will stop at the hal t instruction. ? the data memory contents and registers will maintain their present condition. ? the i/o ports will maintain their present conditions. ? in t he st atus r egister, t he po wer do wn fa g pdf wi ll b e se t, a nd w dt t imeout fa g t o wi ll b e cleared. ? the wdt will be cleared and resume counting if the wdt function is enabled. if the wdt function is disabled, the wdt will be cleared and stopped.
rev. 1.00 40 ? a ??? 0 ?? ? 01 ? rev. 1.00 41 ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu nterin the 0 moe there is only one way for the device to enter the idle0 mode and that is to execute the hal t instruction in the application program with the fhiden bit in scc register equal to 0 and the fsiden b it i n sc c r egister e qual t o 1. w hen t his i nstruction i s e xecuted u nder t he c onditions described above, the following will occur: ? the f h clock will be stopped and the application program will stop at the halt instruction, but the f sub clock will be on. ? the data memory contents and registers will maintain their present condition. ? the i/o ports will maintain their present conditions. ? in t he st atus r egister, t he po wer do wn fa g pdf wi ll b e se t, a nd w dt t imeout fa g t o wi ll b e cleared. ? the wdt will be cleared and resume counting if the wdt function is enabled. if the wdt function is disabled, the wdt will be cleared and stopped. there is only one way for the device to enter the idle0 mode and that is to execute the hal t instruction in the application program with both the fhiden and fsiden bits in the scc register equal to 1. when this instruction is executed under the conditions described above, the following will occur: ? the f h and f sub clocks will be on and the application program will stop at the halt instruction. ? the data memory contents and registers will maintain their present condition. ? the i/o ports will maintain their present conditions. ? in t he st atus r egister, t he po wer do wn fa g pdf wi ll b e se t, a nd w dt t imeout fa g t o wi ll b e cleared. ? the wdt will be cleared and resume counting if the wdt function is enabled. if the wdt function is disabled, the wdt will be cleared and stopped. there is only one way for the device to enter the idle2 mode and that is to execute the hal t instruction in the application program with the fhiden bit in the scc register equal to 1 and the fsiden bit in the scc register equal to 0. when this instruction is executed under the conditions described above, the following will occur: ? the f h clock will be on but the f sub clock will be of f and the applicatio n program will stop at the halt instruction. ? the data memory contents and registers will maintain their present condition. ? the i/o ports will maintain their present conditions. ? in t he st atus r egister, t he po wer do wn fa g pdf wi ll b e se t, a nd w dt t imeout fa g t o wi ll b e cleared. ? the wdt will be cleared and resume counting if the wdt function is enabled. if the wdt function is disabled, the wdt will be cleared and stopped.
rev. 1.00 40 ?a??? 0?? ?01? rev. 1.00 41 ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu tan crrent consierations as the main reason for entering the sleep or idle mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the idle1 and idle2 mode, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. special attention must be made to t he i/ o pi ns on t he de vice. al l hi gh-impedance i nput pi ns m ust be c onnected t o e ither a fxed high or low level as any foating input pins could create internal oscillations and result in increased current consumption. this also applies to the device which has dif ferent package types, as there may be unbonded pins. these must eit her be set up as out puts or if set up as input s must have pul l-high resistors connected. care must also be taken with the loads, which are connected to i/o pins, which are setup as outputs. these should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other cmos inputs. also note that additional standby current will also be required if the lirc oscillator has enabled. in the idle1 and idle2 mode the high speed oscillator is on, if the peripheral function clock source is derived from the high speed oscillator , the additional standby current will also be perhaps in the order of several hundred micro-amps. to minimise power consumption the device can enter the sleep or any idle mode, where the cpu will be switched of f. however , when the device is woken up again, it will take a considerable time for the original system oscillator to restart, stabilise and allow normal operation to resume. after the system enters the sleep or idle mode, it can be woken up from one of various sources listed as follows: ? an external falling edge on port a ? a system interrupt ? a wdt overfow when the device executes the hal t instruction, the pdf fag will be set to 1. the pdf fag will be cleare d to 0 if the device experi ences a system power -up or executes the clear w atchdog t imer instruction. if the system is woken up by a wdt overfow , a w atchdog t imer reset will be initiated and the t o fag will be set to 1. the t o fag is set if a wdt time-out occurs and causes a wake-up that only resets the program counter and stack pointer, other fags remain in their original status. each pin on port a can be setup using the p awu register to permit a negative transition on the pin to wake-up t he syste m. when a port a pin wake-up occurs, the progra m wil l resume exec ution at the i nstruction f ollowing t he halt i nstruction. i f t he sy stem i s wo ken u p by a n i nterrupt, t hen two possible situations may occur . the frst is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the hal t instruction. in this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is fnally enabled or when a stack level becomes free. the other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request flag i s se t hi gh be fore e ntering t he sle ep or idl e mode, t he wa ke-up func tion of t he re lated interrupt will be disabled.
rev. 1.00 4 ? ? a ??? 0 ?? ? 01 ? rev. 1.00 4? ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu atho tier the w atchdog t imer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. the w atchdog t imer clock source is provided by the internal clock, f lirc , which is in turn supplied by the lirc oscillator . the w atchdog t imer source clock is then subdivided by a ratio of 2 8 to 2 18 to give longer timeou ts, the actual value being chosen using the ws2~ws0 bits in the wdtc register . the lirc internal oscillator has an approximate frequency of 32khz and this specified internal clock period can vary with v dd , temperature and process variations. a single register , wdtc, controls the required timeout period as well as the enable/disable and reset mcu operation. name we4 we ? we ? we1 we0 ws ? ws1 ws0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 0 1 1 bit 7~3 : wdt function software control 10101: disable 01010: enable others: reset mcu when these bits are changed by the environmental noise or software setting to reset the microcontroller , the reset operation will be activated after 2~3 f lirc clock cycles and the wrf bit in the rstfc register will be set high. bit 2~0 : wdt time-out period selection 000: 2 8 /f lirc 001: 2 10 /f lirc 010: 2 12 /f lirc 011: 2 14 /f lirc 100: 2 15 /f lirc 101: 2 16 /f lirc 110: 2 17 /f lirc 111: 2 18 /f lirc these t hree b its d etermine t he d ivision r atio o f t he wa tchdog t imer so urce c lock, which in turn determines the time-out period.
rev. 1.00 4? ?a??? 0?? ?01? rev. 1.00 4 ? ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu tfc eister bit 6 5 4 3 0 name lvrf lrf wrf r/w r/w r/w r/w por x 0 0 x unknown bit 7~3 unimplemented, read as 0 bit 2 lvrf : lvr function reset fag described elsewhere. bit 1 lrf : lvr control register software reset fag described elsewhere. bit 0 wrf : wdt control register software reset fag 0: not occur 1: occurred this bit is set high by the wdt control register software reset and cleared by the application program. note that this bit can only be cleared to zero by the application program. the w atchdog t imer ope rates by provi ding a de vice re set whe n i ts t imer ove rfows. t his m eans that i n t he a pplication pro gram a nd dur ing nor mal ope ration t he use r ha s t o st rategically c lear t he watchdog t imer before it overfows to prevent the w atchdog t imer from executing a reset. this is done using the cle ar watchdog instructions. if the program malfunction s for whatever reason, jumps to an unknown location, or enters an endless loop, these clear instructions will not be executed in the correct manner , in which case the w atchdog t imer will overfow and reset the device. there are fve bits, we4~we0, in the wdtc register to of fer the enable/disable control and reset control of the watchdog t imer. the wdt functio n will be disabled when the we4~we0 bits are set to a value of 10101b while the wdt function will be enabled if the we4~we0 bits are equal to 01010b. if the we4~we0 bits are set to any other values, other than 01010b and 10101b, it will reset the device after 2~3 f lirc clock cycles. after power on these bits will have a value of 01010b. 10101b disable 01010b enable any ot ? e ? values reset ? cu wat??dog time? enable/disable cont?ol under norm al progra m ope ration, a w atchdog t imer t ime-out wi ll i nitialise a de vice re set a nd se t the status bit t o. however , if the system is in the sleep or idle mode, when a w atchdog t imer time-out occurs, the t o bit in the status register will be set and only the program counter and stack pointer will be reset. three methods can be adopted to clear the contents of the w atchdog t imer. the frst is a wdt reset, which means a certain value except 01010b and 10101b written into the we4~we0 bit fled, the second is using the w atchdog t imer software clear instruction and the third is via a halt instruction. there is only one method of using software instruction to clear the w atchdog t imer. that is to use the single clr wdt instruction to clear the wdt .
rev. 1.00 44 ? a ??? 0 ?? ? 01 ? rev. 1.00 45 ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu the maximum time out period is when the 2 18 division ratio is selected. as an example, with a 32khz lirc oscillator as its source clock, this will give a maximum watchdog period of around 8 second for the 2 18 division ratio, and a minimum timeout of 7.8ms for the 2 division ration. clr wdt inst?u?tion we4~we0 bits wdtc registe? reset ?cu f lirc clr halt inst?u?tion lirc 8-stage divide? wdt p?es?ale? f lirc /? 8 8-to-1 ?ux ws?~ws0 wdt time-out watchdog timer reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. the most important reset condition is after power is frst applied to the microcontroller . in this case, internal circuitry will ensure that the mi crocontroller, after a short delay , wil l be in a well -defined stat e and ready to execute t he fr st p rogram i nstruction. af ter t his p ower-on r eset, c ertain i mportant i nternal r egisters will be set to defned states before the program commences. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. another type of reset is when the w atchdog t imer overfows and resets. all types of reset operations result in dif ferent register condition s being setup. another reset exists in the form of a low v oltage reset, l vr, where a ful l re set, i s i mplemented i n sit uations where t he power suppl y vol tage fa lls below a certain threshold. reset functions there are several ways in which a microcontroller reset can occur , through events occurring internally. power-on reset the m ost fund amental a nd una voidable re set i s t he one t hat oc curs a fter powe r i s frst a pplied t o the microcontroller . as well as ensuring that the program memory begins execution from the frst memory address, a pow er-on reset als o ensures that certain other registers are preset to known conditions. all the i/o port and port control registers will power up in a high condition ensuring that all i/o ports will be frst set to inputs. vdd powe?-on reset sst time-out t rstd note: t rstd is power-on delay, typical time=50ms power-on reset timing chart
rev. 1.00 44 ?a??? 0?? ?01? rev. 1.00 45 ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu ow oltae eset the micr ocontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. the l vr function is always enabled with a specifc l vr voltag e v lvr . if the supply voltage of the device drops to within a range of 0.9v~v lvr such as might occur when changing the battery , the l vr will automatically reset the device internally and the l vrf bit in the rstfc register will also be set high. for a valid l vr signal, a low supply voltage, i.e., a voltage in the range between 0.9v~v lvr must exist for a time greater than that specifed by t lvr in the lvd/lvr characteristics. if the low supply voltage state does not exceed this value, the l vr will ignore the low supply voltage and will not perform a reset function. the actual v lvr val ue can be selected by the l vs7~lvs0 bits in the l vrc register . if the l vs7~lvs0 bits are changed to some certain values by the environmental noise or software setting, the l vr will reset the device after 2~3 f lirc clock cycles. when this happens, the lrf bit in the rstfc register will be set high. after power on the register will have the value of 01010101b. note that the l vr function will be automatically disabled when the device enters the power down mode. lvr inte?nal reset t rstd + t sst note: t rstd is power-on delay, typical time=50ms ? name lvs7 lvs ? lvs5 lvs4 lvs ? lvs ? lvs1 lvs0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 1 0 1 bit 7~0 lvs7~lvs0 : lvr voltage select 01010101: 2.1v 00110011: 2.55v 10011001: 3.15v 10101010: 3.8v other values: mcu reset (register is reset to por value). when an actual low voltage condit ion occurs, as specifed by one of the four defned lvr voltage values above, an mcu reset will be generated. the reset operation will be a ctivated a fter t he l ow vol tage c ondition ke eps m ore t han a t lvr t ime. in t his situation the register contents will remain the same after such a reset occurs. any register value, other than the four defned l vr values above, will also result in the generation of an mcu reset. the reset operation will be activated after 2~3 f lirc clock cycles. however in this situation the register contents will be reset to the por value. ? name lvrf lrf wrf r/w r/w r/w r/w por x 0 0 x unknown bit 7~3 unimplemented, read as 0 bit 2 lvrf : lvr function reset fag 0: not occur 1: occurred this bit is set high when a specifc low v oltage reset situation condition occurs. this bit can only be cleared to zero by the application program.
rev. 1.00 4 ? ? a ??? 0 ?? ? 01 ? rev. 1.00 47 ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu bit 1 : lvr control register software reset fag 0: not occur 1: occurred this bit is set high if the l vrc register contains any non-defned l vr voltage register values. this in ef fect acts like a software-reset function. this bit can only be cleared to zero by the application program. bit 0 : wdt control register software reset fag described elsewhere. watchdog time-out reset during normal operation the w atchdog time-out reset during normal operation is the same as l vr reset except that the watchdog time-out fag t o will be set high. wdt time-out inte?nal reset t rstd + t sst note: t rstd is power-on delay, typical time=16.7ms wdt time-out reset during normal operation timing chart watchdog time-out reset during sleep or idle mode the w atchdog time-out reset during sleep or idle mode is a little dif ferent from other kinds of re set. mo st of t he c onditions re main unc hanged e xcept t hat t he pro gram count er a nd t he st ack pointer will be cleared to zero and the t o fag will be set high. refer to the a.c. characteristics for details. wdt time-out inte?nal reset t sst wdt time-out reset during sleep or idle mode timing chart reset initial conditions the dif ferent types of reset described af fect the reset fags in dif ferent ways. these fags, known as pdf and t o are located in the status register and are controlled by various microcontroller operations, such as the sleep or idle mode function or w atchdog t imer. the reset fags are shown in the table: to pdf reset conditions 0 0 powe ? -on ? eset u u lvr ? eset du ? ing no ? mal o ? slow ? ode ope ? ation 1 u wdt time-out ? eset du ? ing no ? mal o ? slow ? ode ope ? ation 1 1 wdt time-out ? eset du ? ing idle o ? sleep ? ode ope ? ation note: u stands fo ? un ?? anged the following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. item condition after reset p ? og ? am counte ? reset to ze ? o inte ?? upts all inte ?? upts will be disabled wdt clea ? afte ? ? eset ? wdt begins ? ounting time ? ? odules time ? ? odules will be tu ? ned off input/output po ? ts i/o po ? ts will be setup as inputs sta ? k pointe ? sta ? k pointe ? will point to t ? e top of t ? e sta ? k
rev. 1.00 4? ?a??? 0?? ?01? rev. 1.00 47 ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu the dif ferent kinds of resets all af fect the internal registers of the micr ocontroller in dif ferent ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes how each type of reset affects each of the microcontroller internal registers. iar0 0000 0000 0000 0000 uuuu uuuu ? p0 0000 0000 0000 0000 uuuu uuuu iar1 0000 0000 0000 0000 uuuu uuuu ? p1l 0000 0000 0000 0000 uuuu uuuu ? p1h 0000 0000 0000 0000 uuuu uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu tbhp ---- -xxx ---- -uuu ---- -uuu status xx00 xxxx xx1u uuuu uu11 uuuu iar ? 0000 0000 0000 0000 uuuu uuuu ? p ? l 0000 0000 0000 0000 uuuu uuuu ? p ? h 0000 0000 0000 0000 uuuu uuuu rstfc ---- -x00 ---- -uuu ---- -uuu pb ---- 1111 ---- 1111 ---- uuuu pbc ---- 1111 ---- 1111 ---- uuuu pbpu ---- 0000 ---- 0000 ---- uuuu pbs0 0000 0000 0000 0000 uuuu uuuu pa 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 uuuu uuuu papu 0000 0000 0000 0000 uuuu uuuu pawu 0000 0000 0000 0000 uuuu uuuu pas0 0000 0000 0000 0000 uuuu uuuu pas1 0000 0000 0000 0000 uuuu uuuu scc 000- --00 000- --00 uuu- --uu hircc ---- --01 ---- --01 ---- --uu sadol (adrfs=0) xxxx ---- xxxx ---- xxxx ---- sadol (adrfs=1) xxxx xxxx xxxx xxxx xxxx xxxx sadoh (adrfs=0) xxxx xxxx xxxx xxxx uuuu uuuu sadoh (adrfs=1) ---- xxxx ---- xxxx ---- uuuu sadc0 0000 0000 0000 0000 uuuu uuuu sadc1 0000 0000 0000 0000 uuuu uuuu sledc --00 0000 --00 0000 --uu uuuu integ ---- 0000 ---- 0000 ---- uuuu lvrc 0101 0101 0101 0101 uuuu uuuu lvdc --00 0000 --00 0000 --uu uuuu ocpc0 0000 ---0 0000 ---0 uuuu ---u ocpc1 --00 0000 --00 0000 --uu uuuu ocpda 0000 0000 0000 0000 uuuu uuuu ocpocal 0010 0000 0010 0000 uuuu uuuu ocpccal 0001 0000 0001 0000 uuuu uuuu iicc0 ---- 000- ---- 000- ---- uuu-
rev. 1.00 48 ? a ??? 0 ?? ? 01 ? rev. 1.00 49 ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu eister power n eset t tie-ot oral eration t tie-ot ht iicc1 1000 0001 1000 0001 uuuu uuuu iicd xxxx xxxx xxxx xxxx uuuu uuuu iica 0000 000- 0000 000- uuuu uuu- iictoc 0000 0000 0000 0000 uuuu uuuu intc0 -000 0000 -000 0000 -uuu uuuu intc1 0000 0000 0000 0000 uuuu uuuu intc ? 0000 0000 0000 0000 uuuu uuuu ? fi0 --00 --00 --00 --00 --uu --uu ? fi1 --00 --00 --00 --00 --uu --uu pscr ---- --00 ---- --00 ---- --uu tb0c 0--- -000 0--- -000 u--- -uuu tb1c 0--- -000 0--- -000 u--- -uuu wdtc 0101 0011 0101 0011 uuuu uuuu pt ? 0c0 0000 0--- 0000 0--- uuuu u--- pt ? 0c1 0000 0000 0000 0000 uuuu uuuu pt ? 0dl 0000 0000 0000 0000 uuuu uuuu pt ? 0dh ---- --00 ---- --00 ---- --uu pt ? 0al 0000 0000 0000 0000 uuuu uuuu pt ? 0ah ---- --00 ---- --00 ---- --uu pt ? 0rpl 0000 0000 0000 0000 uuuu uuuu pt ? 0rph ---- --00 ---- --00 ---- --uu pt ? 1c0 0000 0--- 0000 0--- uuuu u--- pt ? 1c1 0000 0000 0000 0000 uuuu uuuu eea ---0 0000 ---0 0000 ---u uuuu eed 0000 0000 0000 0000 uuuu uuuu pt ? 1dl 0000 0000 0000 0000 uuuu uuuu pt ? 1dh ---- --00 ---- --00 ---- --uu pt ? 1al 0000 0000 0000 0000 uuuu uuuu pt ? 1ah ---- --00 ---- --00 ---- --uu pt ? 1rpl 0000 0000 0000 0000 uuuu uuuu pt ? 1rph ---- --00 ---- --00 ---- --uu hvoc ---- 0000 ---- 0000 ---- uuuu hvopc ---- 0000 ---- 0000 ---- uuuu eec ---- 0000 ---- 0000 ---- uuuu note: u stands for unchanged x stands for unknown - stands for unimplemented
rev. 1.00 48 ?a??? 0?? ?01? rev. 1.00 49 ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu nttt ports holtek microcontrollers of fer considerable fexibility on their i/o ports. w ith the input or output designation of e very pi n ful ly unde r use r progra m c ontrol, pul l-high se lections for a ll port s a nd wake-up selections on certain pins, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. the de vice provi des bi directional i nput/output l ines l abeled wi th port na mes p a~pb. t hese i/ o ports are mapped to the ram data memory with specifc addresses as shown in the special purpose data memory table. all of these i/o ports can be used for input and output operations. for input operation, these ports are non-latching, which means the inputs must be ready at the t2 rising edge of instruction mov a, [m], where m denotes the port address. for output operation, all the data is latched and remains unchanged until the output latch is rewritten. pawu pawu7 pawu ? pawu5 pawu4 pawu ? pawu ? pawu1 pawu0 papu papu7 papu4 papu5 papu4 papu ? papu ? papu1 papu0 pa pa7 pa ? pa5 pa4 pa ? pa ? pa1 pa0 pac pac7 pac5 pac5 pac4 pac ? pac ? pac1 pac0 pbpu pbpu ? pbpu ? pbpu1 pbpu0 pb pb ? pb ? pb1 pb0 pbc pbc ? pbc ? pbc1 pbc0 i/o registe? list pull-?ig? resisto?s many produc t applic ations requi re pul l-high resist ors for thei r swi tch inputs usuall y requi ring the use of an external resistor . t o eliminate the need for these external resistors, all i/o pins, when confgured as an input have the capa bility of being connected to an inte rnal pull-high resistor . these pull-high resi stors a re se lected usi ng regi sters p apu~pbpu, a nd a re i mplemented usi ng we ak pmos transistors. note that the pull-high resistor can be controlled by the relevant pull-high control register only when the pin-shared functional pin is selected as a digital input or nmos output. otherwise, the pull-high resistors cannot be enabled. name papu7 papu4 papu5 papu4 papu ? papu ? papu1 papu0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 papu7~papu0 : port a bit 7 ~ bit 0 pull-high control 0: disable 1: enable
rev. 1.00 50 ? a ??? 0 ?? ? 01 ? rev. 1.00 51 ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu pbpu eister bit 6 5 4 3 0 name pbpu ? pbpu ? pbpu1 pbpu0 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~4 unimplemented, read as 0 bit 3~0 pbpu3~pbpu0 : port b bit 3 ~ bit 0 pull-high control 0: disable 1: enable the hal t instruction forces the microcontroller into the sleep or idle mode which preserves power, a feature that is important for battery and other low-power applications. v arious methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the port a pins from high to low . this function is especially suitable for applications that can be woken up via extern al switches. each pin on port a can be selected individually to have this wake-up feature using the pawu register. note t hat t he wa ke-up f unction c an b e c ontrolled b y t he wa ke-up c ontrol r egisters o nly wh en t he pin-shared functio nal pin is selected as general purpose input/output and the mcu enters the power down mode. name pawu7 pawu ? pawu5 pawu4 pawu ? pawu ? pawu1 pawu0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 pawu7~pawu0 : port a bit 7~bit 0 w ake-up control 0: disable 1: enable each i/o port has its own control register known as p ac~pbc, to control the input/output configuration. w ith this control register , each cmos output or input can be reconfigured dynamically under software control. each pin of the i/o ports is directly mapped to a bit in its associated port control register . for the i/o pin to function as an input, the corresponding bit of the control register must be written as a 1. this will then allow the logic state of the input pin to be directly read by instructions. when the corresponding bit of the control register is written as a 0, the i/o pin will be setup as a cmos output. if the pin is currently setup as an output, instructions can still be used to read the output register . however , it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. name pac7 pac5 pac5 pac4 pac ? pac ? pac1 pac0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 bit 7~0 pac7~pa0 : port a bit 7 ~ bit 0 input/output control 0: output 1: input
rev. 1.00 50 ?a??? 0?? ?01? rev. 1.00 51 ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu pbc eister bit 6 5 4 3 0 name pbc ? pbc ? pbc1 pbc0 r/w r/w r/w r/w r/w por 1 1 1 1 bit 7~4 unimplemented, read as 0 bit 3~0 pbc3~pbc0 : port b bit 3 ~ bit 0 input/output control 0: output 1: input the device supports dif ferent source current driving capability for each i/o port. w ith the corresponding selection register , sledc, each i/o port can support four levels of the source current driving capability . users should refer to the d.c. characteristics sectio n to select the desired source current for different applications. name sledc5 sledc4 sledc ? sledc ? sledc1 sledc0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5~4 sledc5~sledc4 : pb3~pb0 source current selection 00: source current=level 0 (min.) 01: source current=level 1 10: source current=level 2 11: source current=level 3 (max.) bit 3~2 sledc3~sledc2 : pa7~pa4 source current selection 00: source current=level 0 (min.) 01: source current=level 1 10: source current=level 2 11: source current=level 3 (max.) bit 1~0 sledc1~sledc0 : pa3~pa0 source current selection 00: source current=level 0 (min.) 01: source current=level 1 10: source current=level 2 11: source current=level 3 (max.) note: users should refer to the d.c. characteristics section to obtain the exact value for dif ferent applications.
rev. 1.00 5 ? ? a ??? 0 ?? ? 01 ? rev. 1.00 5? ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu pin-share fntions the fexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions , many of these diffculties can be overcome. for these pins, the desired function of the multi-functio n i/o pins is selected by a series of registers via the application program control. the limited number of supplied pins in a package can impose restrictions on the amount of functions a certain device can contain. however by allowing the same pins to share several dif ferent functions and providing a means of function selection, a wide range of dif ferent functions can be incorporated into even relatively small package sizes. the device includes port x output function selection register n, labeled as pxsn, which can select the desired functions of the multi-function pin-shared pins. the m ost i mportant p oint t o n ote i s t o m ake sur e t hat t he d esired p in-shared f unction i s p roperly selected and also deselected. t o select the desired pin-shared function, the pin-shared function should frst be correctly selected using the corresponding pin-shared control register . after that the corresponding peripheral functional setting should be confgured and then the peripheral function can be enabled. t o correctly deselect the pin-shared function, the peripheral function should frst be disabled and then the corresponding pin-shared function control register can be modifed to select other pin-shared functions. pas0 pas07 pas0 ? pas05 pas04 pas0 ? pas0 ? pas01 pas00 pas1 pas17 pas1 ? pas15 pas14 pas1 ? pas1 ? pas11 pas10 pbs0 pbs07 pbs0 ? pbs05 pbs04 pbs0 ? pbs0 ? pbs01 pbs00 pin-s?a?ed fun?tion sele?tion registe?s list pas0 registe? bit 7 ? 5 4 ? ? 1 0 name pas07 pas0 ? pas05 pas04 pas0 ? pas0 ? pas01 pas00 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 p as07~pas06 : pa3 pin-shared function selection 00: pa3 01: vref for ocp dac input reference voltage 10: vref for adc and ocp dac input reference voltage 11: an3 bit 5~4 pas05~pas04 : pa2 pin-shared function selection 00: pa2/ptp0i 01: pa2/ptp0i 10: pa2/ptp0i 11: an2 bit 3~2 pas03~pas02 : pa1 pin-shared function selection 00: pa1/ptck0 01: ptp0b 10: ocpi 11: an1 bit 1~0 pas01~pas00 : pa0 pin-shared function selection 00: pa0 01: ptp0 10: pa0 11: an0
rev. 1.00 5? ?a??? 0?? ?01? rev. 1.00 5 ? ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu p eister bit 6 5 4 3 0 name pas17 pas1 ? pas15 pas14 pas1 ? pas1 ? pas11 pas10 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 pas17~pas16 : pa7 pin-shared function selection 00: pa7/ptp1i 01: pa7/ptp1i 10: pa7/ptp1i 11: an7 bit 5~4 pas15~pas14 : pa6 pin-shared function selection 00: pa6/ptck1 01: pa6/ptck1 10: pa6/ptck1 11: an6 bit 3~2 pas13~pas12 : pa5 pin-shared function selection 00: pa5 01: pa5 10: pa5 11: an5 bit 1~0 pas11~pas10 : pa4 pin-shared function selection 00: pa4/int0 01: pa4/int0 10: pa4/int0 11: an4 name pbs07 pbs0 ? pbs05 pbs04 pbs0 ? pbs0 ? pbs01 pbs00 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 pbs07~pbs06 : pb3 pin-shared function selection 00: pb3 01: scl 10: pb3 11: pb3 bit 5~4 pbs05~pbs04 : pb2 pin-shared function selection 00: pb2 01: sda 10: pb2 11: pb2 bit 3~2 pbs03~pbs02 : pb1 pin-shared function selection 00: pb1 01: ptp1b 10: pb1 11: pb1 bit 1~0 pbs01~pbs00 : pb0 pin-shared function selection 00: pb0/int1 01: ptp1 10: pb0/int1 11: pb0/int1
rev. 1.00 54 ? a ??? 0 ?? ? 01 ? rev. 1.00 55 ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu pin trtres the accompanying diagrams illustrate the internal structures of some generic i/o pin types. as the exact logical construction of the i/o pin will dif fer from these drawings, they are supplied as a guide only to assist with the functional understanding of the i/o pins. the wide range of pin-shared structures does not permit all types to be shown. ? u x vdd cont?ol bit data bit data bus w?ite cont?ol registe? c?ip reset read cont?ol registe? read data registe? w?ite data registe? system wake-up wake-up sele?t pa only i/o pin weak pull-up pull-?ig? registe? sele?t q d ck q d ck q q s s gene?i? input/output st?u?tu?e analog input sele?to? ? u x vdd cont?ol bit data bit data bus w?ite cont?ol registe? c?ip reset read cont?ol registe? read data registe? w?ite data registe? to a/d conve?te? a/d input po?t weak pull-up pull-?ig? registe? sele?t q d ck q d ck q q s s sacs?~sacs0 a/d input/output st?u?tu?e
rev. 1.00 54 ?a??? 0?? ?01? rev. 1.00 55 ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu prorain consierations within the user program, one of the frst things to consider is port initi alisation. after a reset, all of the i/o data and port control registers will be set high. this means that all i/o pins will default to an i nput st ate, t he l evel of whi ch de pends on t he ot her c onnected c ircuitry a nd whe ther pul l-high selections have been chosen. if the port control registers, p ac~pbc, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers, p a~pb, are frst programmed. selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register o r b y p rogramming i ndividual b its i n t he p ort c ontrol re gister u sing t he set [m ].i a nd clr [m ].i i nstructions. not e t hat when usi ng t hese bi t c ontrol i nstructions, a re ad-modify-write operation takes place. the microcontroller must frst read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. port a has the additional capability of providing wake-up functions. when the device is in the sleep or idle mode, various methods are available to wake the device up. one of these is a high to low transition of any of the port a pins. single or multiple pins on port a can be setup to have this function. one of the most fundamental functions in any microcontroller device is the ability to control and measure time. t o implement time related functions the device includes several t imer modules, abbreviated t o t he na me t m. t he t ms a re m ulti-purpose t iming un its a nd se rve t o pr ovide operations such as t imer/counter, input capture, compare match output and single pulse output as we ll a s be ing t he fun ctional uni t for t he ge neration of pw m si gnals. e ach of t he t ms ha s t wo individual interrupts. the addition of input and output pins for each tm ensures that users are provided with timing units with a wide and fexible range of features. the g eneral f eatures o f t he pe riodic t ype t m a re d escribed h ere wi th m ore d etailed i nformation provided in the periodic tm section. the device contains two periodic type tms having a reference name of ptm0 and ptm1. the common features to the periodic tms will be described in this section and the detailed operation will be described in the corresponding sections. the main features of the ptm are summarised in the accompanying table. time ? /counte ? i/p captu ? e compa ? e ? at ?? output pw ? c ? annels 1 single pulse output 1 pw ? alignment edge pw ? adjustment pe ? iod & duty duty o ? pe ? iod t? fun?tion summa?y t? ope?ation the periodic type tms of fer a diverse range of functions, from simple timing operations to pwm signal generation. the key to understanding how the tm operates is to see it in terms of a fre e runni ng c ounter who se va lue i s t hen c ompared wi th t he va lue of pre -programmed i nternal comparators. when the free running counter has the same value as the pre-programmed comparator , known a s a c ompare m atch si tuation, a t m i nterrupt si gnal wi ll be ge nerated whi ch c an c lear t he counter a nd pe rhaps a lso c hange t he c ondition of t he t m ou tput pi n. t he i nternal t m c ounter i s driven by a user selectable clock source, which can be an internal clock or an external pin.
rev. 1.00 5 ? ? a ??? 0 ?? ? 01 ? rev. 1.00 57 ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu tm clo ore the clock source which drives the main counter in the tm can originate from various sources. the selection of the required clock source is implemented using the ptnck2~ptnck0 bits in the ptmn control registers. the clock source can be a ratio of the system clock f sys or the internal high clock f h , the f sub clock source or the external ptckn pin. the ptckn pin clock source is used to allow an external signal to drive the tm as an external clock source or for event counting. the periodic t ype tms have two internal interrupts, one for each of the internal comparator a or comparator p , whi ch ge nerate a t m i nterrupt whe n a c ompare m atch c ondition oc curs. w hen a t m interrupt is generated it can be used to clear the counter and also to change the state of the tm output pin. each of the tms has two tm input pin, with the label ptckn and ptpni. the ptmn input pin, ptckn, is essentially a clock source for the ptmn and is selected using the ptnck2~ptnck0 bits in the ptmnc0 register . this external tm input pin allows an external clock source to drive the internal tm. the ptckn input pin can be chosen to have either a rising or falling active edge. the ptckn pin is also used as the external trigger input pin in single pulse output mode for the ptmn. the other ptmn input pin, ptpni, is the capture input whose active edge can be a rising edge, a falling edge or both rising and fallin g edges and the active edge transit ion type is selected using the ptnio1~ptnio0 bits in the ptmnc1 register . there is another capture input, ptckn, for ptmn capture input mode, which can be used as the external trigger input source except the ptpni pin. the tms each have two output pins, ptpn and ptpnb. the ptpnb is the inverted signal of the ptpn output. the tm output pins can be selected using the corresponding pin-shared function selection bits described i n t he pi n-shared func tion se ction. whe n t he tm i s i n t he com pare ma tch out put mode , these pins can be controlled by the tm to switch to a high or low level or to toggle when a compare match situation occurs. the external ptpn or ptpnb output pin is also the pin where the tm generates the pwm output waveform. as the tm output pins are pin-shared with other functions, the tm output function must frst be setup using relevant pin-shared function selection register. ptck0 ? ptp0i ptp0 ? ptp0b ptck1 ? ptp1i ptp1 ? ptp1b t? exte?nal pins t? input/output pin sele?tion selecting t o ha ve a t m i nput/output or whe ther t o re tain i ts ot her sha red func tion i s i mplemented using t he r elevant p in-shared f unction se lection r egisters, wi th t he c orresponding se lection b its i n each pin-shared function register corresponding to a tm input/output pin. confguring the selection bits correctly will setup the corresponding pin as a tm input/output. the details of the pin-shared function selection are described in the pin-shared function section. pt?n ptckn ptpn ptpni ccr ?aptu?e input ccr output ptpnb pt? fun?tion pin cont?ol blo?k diag?am (n=0 o? 1)
rev. 1.00 5? ?a??? 0?? ?01? rev. 1.00 57 ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu prorain consierations the tm counter registers and the capture/compare ccra and ccrp registers, being 10-bit, all have a low and high byte structure. the high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buf fer, reading or writing to these register pairs must be carried out in a specifc way . the important point to note is that data transfer to and from the 8-bit buf fer and its re lated l ow byt e onl y t akes pl ace whe n a wri te or re ad ope ration t o i ts c orresponding hi gh byt e is e xecuted. as t he c cra a nd c crp r egisters a re i mplemented i n t he wa y sh own i n t he f ollowing diagram and accessing the register is carried out in a specifc way described above, it is recommended to use the mov instruction to access the ccra and ccrp low byte registers, named ptmnal and ptmnrpl, usi ng t he fol lowing a ccess proce dures. ac cessing t he ccra or ccrp l ow byt e regi ster without following these access procedures will result in unpredictable values. data bus 8-bit buffe? pt?ndh pt?ndl pt?nah pt?nal pt?n counte? registe? (read only) pt?n ccra registe? (read/w?ite) pt?nrph pt?nrpl pt?n ccrp registe? (read/w?ite) the following steps show the read and write procedures: ? writing data to ccra or ccrp ? step 1. w rite data to low byte ptmnal or ptmnrpl C note that here data is only written to the 8-bit buffer. ? step 2. w rite data to high byte ptmnah or ptmnrph C here data is written directly to the high byte registers and simultaneously data is latched from the 8-bit buffer to the low byte registers. ? reading data from the counter registers and ccra or ccrp ? step 1. read data from the high byte ptmndh, ptmnah or ptmnrph C here data is read directly from the high byte registers and simultaneously data is latched from the low byte register into the 8-bit buffer. ? step 2. read data from the low byte ptmndl, ptmnal or ptmnrpl C this step reads data from the 8-bit buffer.
rev. 1.00 58 ? a ??? 0 ?? ? 01 ? rev. 1.00 59 ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu perioi te tm ptm the pe riodic t ype t m c ontains fv e o perating m odes, wh ich a re c ompare ma tch ou tput, t imer/ event counter , capture input, single pulse output and pwm output modes. the periodic tm can be controlled with two external input pins and can drive two external output pins. ptckn 10-bit count-up counte? 10-bit compa?ato? p ccrp 10-bit compa?ato? a output cont?ol pola?ity cont?ol pin cont?ol ptpn ccra edge dete?to? ptpni pin cont?ol ptpnb ptncclr f sys f sys /4 f h /?4 f h /1? f sub ptnck?~ptnck0 ptnon ptnpau compa?ato? a ?at?? compa?ato? p ?at?? counte? clea? ptnoc ptn?1? ptn?0 ptnio1? ptnio0 pt?naf inte??upt pt?npf inte??upt ptnpol pxsn ptnio1? ptnio0 f sub pxsn ptncapts 000 001 010 011 100 101 110 111 b0~b9 b0~b9 0 1 1 0 pe?iodi? type t? blo?k diag?am (n=0 o? 1) pe?iodi? t? ope?ation the periodic t ype tm core is a 10-bit count-up counter which is driven by a user selectable internal or e xternal c lock sourc e. t here a re a lso t wo i nternal c omparators wi th t he na mes, com parator a and comparator p . these comparators will compare the value in the counter with ccrp and ccra registers. the ccrp comparator is 10-bit wide. the onl y way of changing the value of the 10-bit counte r using the appl ication program , is to clear the counter by changing the ptnon bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur , a ptmn interrupt signal will also usually be generated. the periodic type tm can operate in a number of dif ferent operational modes, can be driven by dif ferent clock sources including an input pin and can also control more than one output pin. all operating setup conditions are selected using relevant internal registers. overall operation of the periodic t ype tm is controlled using a series of registers. a read only register pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store the int ernal 10-bit ccra val ue and ccrp val ue. the rem aining two registers are control registers which setup the different operating and control modes. pt ? nc0 ptnpau ptnck ? ptnck1 ptnck0 ptnon pt ? nc1 ptn ? 1 ptn ? 0 ptnio1 ptnio0 ptnoc ptnpol ptncapts ptncclr pt ? ndl d7 d ? d5 d4 d ? d ? d1 d0 pt ? ndh d9 d8 pt ? nal d7 d ? d5 d4 d ? d ? d1 d0 pt ? nah d9 d8 pt ? nrpl d7 d ? d5 d4 d ? d ? d1 d0 pt ? nrph d9 d8 10-bit pe?iodi? t? registe? list (n=0 o? 1)
rev. 1.00 58 ?a??? 0?? ?01? rev. 1.00 59 ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu ptmnc0 eister bit 6 5 4 3 0 name ptnpau ptnck ? ptnck1 ptnck0 ptnon r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7 ptnpau : ptmn counter pause control 0: run 1: pause the c ounter c an be pa used by se tting t his bi t hi gh. cl earing t he bi t t o z ero re stores normal counter operation. when in a pause condition the ptmn will remain powered up a nd c ontinue t o c onsume po wer. t he c ounter wi ll re tain i ts re sidual va lue whe n this bit changes from low to high and res ume counting from this value w hen the bit changes to a low value again. bit 6~4 ptnck2~ptnck0 : select ptmn counter clock 000: f /4 001: f 010: f h /16 011: f h /64 100: f 101: f 110: ptck rising edge clock 111: ptck falling edge clock these three bits are used to select the clock source for the ptmn. the external pin clock source can be chosen to be active on the rising or falling edge. the clock source is the system clock, while f h and f are other internal clocks, the details of which can be found in the oscillator section. bit 3 ptnon : ptmn counter on/off control 0: off 1: on this bit controls the overall on/of f function of the ptmn. setting the bit high enables the counter to run, clearing the bit disables the ptmn. clearing this bit to zero will stop the counter from counting and turn of f the ptmn which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low , the internal counter will retain its residual value until the bit returns high again. if the ptmn is in the compare match output mode, pwm output mode or single pulse output mode then the ptmn output pin will be reset to its initial condition, as specifed by the ptnoc bit, when the ptnon bit changes from low to high. bit 2~0 unimplemented, read as 0
rev. 1.00 ? 0 ? a ??? 0 ?? ? 01 ? rev. 1.00 ?1 ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu ptmnc eister bit 6 5 4 3 0 name ptn ? 1 ptn ? 0 ptnio1 ptnio0 ptnoc ptnpol ptncapts ptncclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 ptnm1~ptnm0 : select ptmn operating mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: t imer/counter mode these bits setup the required operating mode for the ptmn. t o ensure reliable operation the ptmn should be switched of f before any changes are made to the ptnm1 and ptnm0 bits. in the t imer/counter mode, the ptmn output pin control must be disabled. bit 5~4 ptnio1~ptnio0 : select ptmn external pin ptpn or ptpni/ptckn function compare match output mode 00: no change 01: output low 10: output high 11: t oggle output pwm mode/single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of ptpni or ptckn 01: input capture at falling edge of ptpni or ptckn 10: input capture at falling/rising edge of ptpni or ptckn 11: input capture disabled timer/counter mode unused these two bits are used to determine how the ptmn output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the ptmn is running. in the compare match output mode, the ptnio1 and ptnio0 bits determine how the ptmn output pin changes state when a compare match occurs from the comparator a. the ptmn output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the ptmn output pin should be setup us ing the ptnoc bit in the ptmnc1 regis ter. note that the output level requested by the ptnio1 and ptnio0 bits must be dif ferent from the initial value setup using the ptnoc bit otherwise no change will occur on the ptmn output pin when a compare match occurs. after the ptmn output pin changes state, it can be reset to its initial level by changing the level of the ptnon bit from low to high. in the pwm mode, the pt nio1 and pt nio0 bits determi ne how the pt mn out put pin changes state when a certain compare match condition occurs. the pwm output function i s m odified b y c hanging t hese t wo b its. i t i s n ecessary t o o nly c hange t he values of t he pt nio1 a nd pt nio0 bi ts onl y a fter t he t m ha s be en swi tched of f. unpredictable pwm outputs will occur if the ptnio1 and ptnio0 bits are changed when the ptmn is running.
rev. 1.00 ?0 ?a??? 0?? ?01? rev. 1.00 ? 1 ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu bit 3 : ptmn ptpn output control bit compare match output mode 0: initial low 1: initial high pwm mode/single pulse output mode 0: active low 1: active high this is the output control bit for the ptmn output pin. its operation depends upon whether ptmn is being used in the compare match output mode or in the pwm mode/single pulse output mode. it has no ef fect if the ptmn is in the t imer/counter mode. in the compare match output mode it determines the logic level of the ptmn output pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 : ptmn ptpn output polarity control 0: non-invert 1: invert this bit controls the polarity of the ptpn output pin. when the bit is set high the ptmn output pin will be inverted and not inverted when the bit is zero. it has no ef fect if the ptmn is in the t imer/counter mode. bit 1 : ptmn capture t rigger source selection 0: from ptpni pin 1: from ptckn pin bit 0 : select ptmn counter clear condition 0: ptmn comparator p match 1: ptmn comparator a match this bi t i s use d t o se lect t he m ethod whi ch c lears t he c ounter. re member t hat t he periodic t m c ontains t wo c omparators, com parator a a nd com parator p , e ither of which can be selected to clear the internal counter . w ith the ptncclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low , the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow . a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the ptncclr bit is not used in the pwm mode, single pulse or capture input mode. ptmndl register bit 7 6 5 4 3 2 1 0 name d7 d ? d5 d4 d ? d ? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 : ptmn counter low byte register bit 7 ~ bit 0 ptmn 10-bit counter bit 7 ~ bit 0 ptmndh register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r r por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 : ptmn counter high byte register bit 1 ~ bit 0 ptmn 10-bit counter bit 9 ~ bit 8
rev. 1.00 ?? ? a ??? 0 ?? ? 01 ? rev. 1.00 ?? ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu ptmn eister bit 6 5 4 3 0 name d7 d ? d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : ptmn ccra low byte register bit 7 ~ bit 0 ptmn 10-bit ccra bit 7 ~ bit 0 name d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 d9~d8 : ptmn ccra high byte register bit 1 ~ bit 0 ptmn 10-bit ccra bit 9 ~ bit 8 name d7 d ? d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : ptmn ccrp low byte register bit 7 ~ bit 0 ptmn 10-bit ccrp bit 7 ~ bit 0 name d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 d9~d8 : ptmn ccrp high byte register bit 1 ~ bit 0 ptmn 10-bit ccrp bit 9 ~ bit 8
rev. 1.00 ?? ?a??? 0?? ?01? rev. 1.00 ?? ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu perioi te tm eratin moes the standard t ype tm can operate in one of fve operating modes, compare match output mode, pwm output mode, single pulse output mode, capture input mode or t imer/counter mode. the operating mode is selected using the ptnm1 and ptnm0 bits in the ptmnc1 register. to select this mode, bits ptnm1 and ptnm0 in the ptmnc1 register , should be set to 00 respectively. in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow , a compare match from comparator a and a compare match from comparator p . when the ptncclr bit is low , there are two ways in which the counter can be cleared. one is when a compare match from comparator p , the other is when the ccrp bits are all zero which allows the counter to overfow . here both ptmnaf and ptmnpf interrupt request fags for comparator a and comparator p respectively, will both be generated. if the ptncclr bit in the ptmnc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however , here only the ptmnaf interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when ptncclr is high no ptmnpf interrupt request fag will be generated. in the compare match output mode, the ccra can not be cleared to zero. if the ccra bits are all zero, the counter will overfow when its reaches its maximum 10-bit, 3ff hex, value, however here the ptmnaf interrupt request fag will not be generated. as the name of the mode suggests, after a comparison is made, the ptmn output pin, will change state. the ptmn output pin condition however only changes state when a ptmnaf interrupt request fag is generated after a compare match occurs from comparator a. the ptmnpf interrupt request fag, generated from a compare match occurs from comparator p , will have no ef fect on the ptmn output pin. the way in which the ptmn output pin changes state are determined by the condition of the ptnio1 and ptnio0 bits in the ptmnc1 register . the ptmn output pin can be selected using the pt nio1 a nd pt nio0 bi ts t o go hi gh, t o go l ow or t o t oggle fr om i ts pre sent c ondition whe n a compare match occurs from comparator a. the initial condition of the ptmn output pin, which is setup afte r the ptnon bit changes from low to high, is setup using the ptnoc bit. note that if the ptnio1 and ptnio0 bits are zero then no pin change will take place.
rev. 1.00 ? 4 ? a ??? 0 ?? ? 01 ? rev. 1.00 ?5 ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu conter ale 0x?ff ccrp ccra ptnon ptnpau ptnpol ccrp int. flag pt?npf ccra int. flag pt?naf pt?n o/p pin time ccrp=0 ccrp > 0 counte? ove?flow ccrp > 0 counte? ?lea?ed by ccrp value pause resume stop counte? resta?t ptncclr = 0 ptn?[1:0] = 00 output pin set to initial level low if ptnoc=0 output toggle wit? pt?naf flag note ptnio [1:0] = 10 a?tive hig? output sele?t he?e ptnio [1:0] = 11 toggle output sele?t output not affe?ted by pt?naf flag. remains hig? until ?eset by ptnon bit output pin reset to initial value output ?ont?olled by ot?e? pin-s?a?ed fun?tion output inve?ts w?en ptnpol is ?ig? compa?e ?at?? output ?ode ? note: 1. w ith ptncclr=0 a comparator p match will clear the counter 2. the ptmn output pin is controlled only by the ptmnaf fag 3. the output pin is reset to its initial state by a ptnon bit rising edge
rev. 1.00 ?4 ?a??? 0?? ?01? rev. 1.00 ? 5 ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu conter ale 0x?ff ccrp ccra ptnon ptnpau ptnpol ccrp int. flag pt?npf ccra int. flag pt?naf pt?n o/p pin time ccra=0 ccra = 0 counte? ove?flow ccra > 0 counte? ?lea?ed by ccra value pause resume stop counte? resta?t ptncclr = 1 ptn?[1:0] = 00 output pin set to initial level low if ptnoc=0 output toggle wit? pt?naf flag note ptnio [1:0] = 10 a?tive hig? output sele?t he?e ptnio [1:0] = 11 toggle output sele?t output not affe?ted by pt?naf flag. remains hig? until ?eset by ptnon bit output pin reset to initial value output ?ont?olled by ot?e? pin-s?a?ed fun?tion output inve?ts w?en ptnpol is ?ig? pt?npf not gene?ated no pt?naf flag gene?ated on ccra ove?flow output does not ??ange compa?e ?at?? output ?ode ? note: 1. w ith ptncclr=1 a comparator a match will clear the counter 2. the ptmn output pin is controlled only by the ptmnaf fag 3. the output pin is reset to its initial state by a ptnon bit rising edge 4. a ptmnpf fag is not generated when ptncclr=1
rev. 1.00 ?? ? a ??? 0 ?? ? 01 ? rev. 1.00 ?7 ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu tierconter moe to se lect t his mode , bi ts pt nm1 and pt nm0 i n t he pt mnc1 regi ster should be se t t o 1 1 respectively. the t imer/counter mode operates in an identical way to the compare match output mode generating the same interrupt flags. the exception is that in the t imer/counter mode the tm output pin is not used. therefore the above description and t iming diagrams for the compare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. to select this mode, bits ptnm1 and ptnm0 in the ptmnc1 register should be set to 10 respectively. the pwm function within the ptmn is useful for applica tions which require functions such as motor control, heating control, illumination control etc. by providing a signal of fixed frequency but of varying duty cycle on the ptmn output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform is extre mely fexible. in the pwm output mode, the ptncclr bit has no ef fect on the pwm operation. both of the ccra and ccrp registers are used to generate the pwm waveform, one register is used to clear the internal counter and thus control the pwm waveform frequency , while the other one is used to control the duty cycle. the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt fag, one for each of the ccra and ccrp , will be generated when a compare match occurs from either comparator a or comparator p . the ptnoc bit in the ptmnc1 register is used to select the required polari ty of the pwm waveform whi le the two ptnio1 and ptnio0 bi ts are used to enable the pwm output or to force the ptmn output pin to a fxed high or low level. the ptnpol bit is used to reverse the polarity of the pwm output waveform. ? pe ? iod 1~10 ?? 10 ? 4 duty ccra if f sys =12mhz, ptmn clock source select f sys /4, ccrp=512 and ccra=128, the ptmn pwm output frequency=(f sys /4)/512=f sys /2048=5.8594khz, duty=128/(2 256)=25%. if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%.
rev. 1.00 ?? ?a??? 0?? ?01? rev. 1.00 ? 7 ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu conter ale ccrp ccra ptnon ptnpau ptnpol ccrp int. flag pt?npf ccra int. flag pt?naf pt?n o/p pin (ptnoc=1) time counte? ?lea?ed by ccrp pause resume counte? stop if ptnon bit low counte? reset w?en ptnon ?etu?ns ?ig? ptn?[1:0] = 10 pw? duty cy?le set by ccra pw? ?esumes ope?ation output ?ont?olled by ot?e? pin-s?a?ed fun?tion output inve?ts w?en ptnpol = 1 pw? pe?iod set by ccrp pt?n o/p pin (ptnoc=0) pw? output ?ode (n=0 o? 1) note: 1. counter cleared by ccrp 2. a counter clear sets the pwm period 3. the internal pwm function continues running even when ptnio[1:0]=00 or 01 4. the ptncclr bit has no infuence on pwm operation
rev. 1.00 ? 8 ? a ??? 0 ?? ? 01 ? rev. 1.00 ?9 ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu inle plse moe to select this mode, bits ptnm1 and ptnm0 in the ptmnc1 register should be set to 10 respectively and also the ptnio1 and ptnio0 bits should be set to 1 1 respectively . the single pulse output mode, as the name suggests, will generate a single shot pulse on the ptmn output pin. the t rigger f or t he p ulse o utput l eading e dge i s a l ow t o h igh t ransition o f t he pt non b it, wh ich can be implement ed using the application program. however in the single pulse mode, the ptnon bit can also be made to automatically change from low to high using the external ptckn pin, which will in turn initiate the single pulse output. when the ptnon bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. the ptnon bit should remain high when the pulse is in its active state. the generated pulse trailing edge will be generated when the ptnon bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from comparator a. however a compa re match from comparator a will also automatically clear the ptnon bit and thus generate the single pulse output trailing edge. in this way the ccra value can be used to control the pulse width. a compare match from comparator a will also generate a ptmn interrupt. the counter can only be res et back to zero w hen the ptno n bit changes from low to high w hen the counter restarts. in the single pulse mode ccrp is not used. the ptncclr bit is not used in this mode. ptnon bit 0 1 s/w command set ptnon o? ptckn pin t?ansition ptnon bit 1 0 ccra t?ailing edge s/w command clr ptnon o? ccra compa?e ?at?? ptpn output pin pulse widt? = ccra value ccra leading edge single pulse gene?ation (n=0 o? 1)
rev. 1.00 ?8 ?a??? 0?? ?01? rev. 1.00 ? 9 ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu conter ale ccrp ccra ptnon ptnpau ptnpol ccrp int. flag pt?npf ccra int. flag pt?naf pt?n o/p pin (ptnoc=1) time counte? stopped by ccra pause resume counte? stops by softwa?e counte? reset w?en ptnon ?etu?ns ?ig? ptn?[1:0] = 10 ptnio[1:0] = 11 pulse widt? set by ccra output inve?ts w?en ptnpol = 1 no ccrp inte??upts gene?ated pt?n o/p pin (ptnoc=0) ptckn pin softwa?e t?igge? clea?ed by ccra mat?? ptckn pin t?igge? auto. set by ptckn pin softwa?e t?igge? softwa?e clea? softwa?e t?igge? softwa?e t?igge? single pulse ?ode (n=0 o? 1) note: 1. counter stopped by ccra 2. ccrp is not used 3. the pulse is triggered by the ptckn pin or by setting the ptnon bit high 4. a ptckn pin active edge will automatically set the ptnon bit high 5. in the single pulse mode, ptnio[1:0] must be set to 11 and cannot be changed.
rev. 1.00 70 ? a ??? 0 ?? ? 01 ? rev. 1.00 71 ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu catre nt moe to select this mode bits ptnm1 and ptnm0 in the ptmnc1 register should be set to 01 respectively. this mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. the external signal i s sup plied on t he pt pni or pt ckn p in whi ch i s se lected usi ng t he pt ncapts b it i n t he ptmnc1 register . the input pin active edge can be either a rising edge, a falling edge or both rising and fallin g edges; the active edge transition type is selected using the ptnio1 and ptnio0 bits in the ptmnc1 register . the counter is started when the ptnon bit changes from low to high which is initiated using the application program. when the required edge transition appears on the ptpni or ptckn pin the present value in the counter will be latched into the ccra registers and a ptmn interrupt generated. irrespective of what events occur on the ptpni or ptckn pin, the counter will continue to free run until the ptnon bit changes from high to low . when a ccrp compare match occurs the counter will reset back to zero; in this way the ccrp value can be used to control the maximum counter value. when a ccrp compare match occurs from comparator p , a ptmn interrupt will also be generated. counting the number of overfow interrupt signals from the ccrp can be a useful method in measuring long pulse widths. the ptnio1 and ptnio0 bits can select the active trigger edge on the ptpni or ptckn pin to be a rising edge, falling edge or both edge types. if the ptnio1 and ptnio0 bits are both set high, then no capture operation will take place irrespective of what happens on the ptpni or ptckn pin, however it must be noted that the counter will continue to run. as the ptpni or ptckn pin is pin shared with other functions, care must be taken if the ptmn is in the capture input mode. this is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. the ptncclr, ptnoc and ptnpol bits are not used in this mode.
rev. 1.00 70 ?a??? 0?? ?01? rev. 1.00 71 ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu conter ale yy ccrp ptnon ptnpau ccrp int. flag pt?npf ccra int. flag pt?naf ccra value time counte? ?lea?ed by ccrp pause resume counte? reset ptn?[1:0] = 01 pt?n captu?e pin ptpni o? ptckn xx counte? stop ptnio [1:0] value a?tive edge a?tive edge a?tive edge 00 - rising edge 01 - falling edge 10 - bot? edges 11 - disable captu?e xx yy xx yy captu?e input ?ode (n=0 o? 1) note: 1. ptnm[1:0]=01 and active edge set by the ptnio[1:0] bits 2. a ptmn capture input pin active edge transfers the counter value to ccra 3. ptncclr bit not used 4. no output function C ptnoc and ptnpol bits are not used 5. ccrp determin es the counter value and the counter has a maximum count value when ccrp is equal to zero.
rev. 1.00 7 ? ? a ??? 0 ?? ? 01 ? rev. 1.00 7? ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu nalo to iital conerter the need to interface to real world analog signals is a common requirement for many electronic systems. however , to properly process these signals by a microcontroller , they must first be converted into digital signals by a/d converters. by integrating the a/d conversion electronic circuitry into the microcontroller , the need for external components is reduced signifcantly with the corresponding follow-on benefts of lower costs and reduced component space requirements. this device contains a multi-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into a 12-bi t di gital value. it also can convert the internal signals, the bandgap reference voltage v bg and the over current protection analog output signal ocp ao, into a 12-bit digital value. the externa l or internal analog signal to be converted is determined by the sains2~sains0 bits together with the sacs3~sac s0 bits. when the external analog signal is to be converted, the corresponding pin-shared control bits should frst be properly confgured and then desired external channel input should be selected using the sains2~sains0 and sacs3~sacs0 bits. note that when the internal analog signal is to be converted, the pin-shared control bits should also be properly confgured except the sains and sacs bit felds. more detailed information about the a/d input signal is described in the a/d converter control registers and a/d converter input signals sections respectively. 8: an0~an7 ? : v bg ? ocpao sains ? ~sains0 ? sacs ? ~sacs0 the accompanying block diagram shows the overall internal structure of the a/d converter , together with its associated registers. pin-s?a?ed sele?tion sacs?~sacs0 sains?~sains0 a/d conve?te? start adbz adcen av ss ? n (n=0~7) f sys sacks?~sacks0 av dd vref savrs1~savrs0 adcen a/d refe?en?e voltage a/d data registe?s adrfs an0 an1 an7 an5 an? an4 an? an? v bg ocpao sadol sadoh a/d clo?k a/d conve?te? st?u?tu?e
rev. 1.00 7? ?a??? 0?? ?01? rev. 1.00 7 ? ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu conerter eister esrition overall operation of the a/d converter is controlled using several registers. a read only register pair exists to store the a/d converter data 12-bit value. the remaining two registers are control registers which setup the operating and control function of the a/d converter. sadol(adrfs=0) d ? d ? d1 d0 sadol(adrfs=1) d7 d ? d5 d4 d ? d ? d1 d0 sadoh(adrfs=0) d11 d10 d9 d8 d7 d ? d5 d4 sadoh(adrfs=1) d11 d10 d9 d8 sadc0 start adbz adcen adrfs sacs ? sacs ? sacs1 sacs0 sadc1 sains ? sains1 sains0 savrs1 savrs0 sacks ? sacks1 sacks0 a/d conve?te? registe? list a/d conve?te? data registe?s C sadol? sadoh as t his d evice c ontains a n i nternal 1 2-bit a/ d c onverter, i t r equires t wo d ata r egisters t o st ore t he converted value. these are a high byte register , known as sadoh, and a low byte register , known as sadol. after the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. as only 12 bits of the 16-bit register space is ut ilised, t he form at i n whi ch t he da ta i s st ored i s c ontrolled by t he adrfs bi t i n t he sadc0 register as shown in the accompany ing table. d0~d1 1 are the a/d conversion result data bits. any unused bits will be read as zero. note that a/d data registers contents will be unchanged if the a/d converter is disabled. 0 d11 d10 d9 d8 d7 d ? d5 d4 d ? d ? d1 d0 0 0 0 0 1 0 0 0 0 d11 d10 d9 d8 d7 d ? d5 d4 d ? d ? d1 d0 a/d data registe?s a/d conve?te? cont?ol registe?s C sadc0? sadc1 to control the function and operatio n of the a/d converter , two control registers known as sadc0 and sadc1 are provided. these 8-bit registers define functions such as the selection of which analog channel is connected to the internal a/d converter , the digitise d data format, the a/d clock source as well as controlling the start function and monitoring the a/d converter busy status. as the device contains only one actual analog to digital converter hardware circuit, each of the external or i nternal a nalog si gnal i nputs m ust be ro uted t o t he c onverter. t he sacs3~ sacs0 bi ts i n t he sadc0 register are used to determine which external channel input is selected to be converted. the sains2~sains0 bits in the sadc1 register are used to determine that the analog signal to be converted comes from the internal analog signal or external analog channel input. the relev ant pin-shared function selection bits determine which pins on i/o ports are used as analog inputs for the a/d converter input and which pins are not to be used as the a/d converter input. when the pin is selected to be an a/d input, its original function whether it is an i/o or other pin- shared function will be removed. in addition, any internal pull-high resistor connected to the pin will be automatically removed if the pin is selected to be an a/d converter input.
rev. 1.00 74 ? a ??? 0 ?? ? 01 ? rev. 1.00 75 ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu c0 eister bit 6 5 4 3 0 name start adbz adcen adrfs sacs ? sacs ? sacs1 sacs0 r/w r/w r r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 start : start the a/d conversion 010: start this bit is used to initiate an a/ d conversion process. the bit is normally low but if set high and then cleared low again, the a/d converter will initiate a conversion process. when the bit is set high the a/d converter will be reset. bit 6 adbz : a/d converter busy fag 0: no a/d conversion is in progress 1: a/d conversion is in progress this read only fag is us ed to indicate w hether the a /d convers ion is in progress or not. when the st art bit is set from low to high and then to low again, the adbz fag will be set to 1 to indicate that the a/d conversion is initiated. the adbz fag will be cleared to 0 after the a/d conversion is complete. bit 5 adcen : a/d converter function enable control 0: disable 1: enable this bit controls the a/d internal function. this bit should be set to one to enable the a/ d c onverter. if t he bi t i s se t l ow, t hen t he a/ d c onverter wi ll be swi tched of f reducing the device power consumption. when the a/d converter function is disabled, the contents of the a/d data register pair known as sadoh and sadol will be unchanged. bit 4 adrfs : a/d converter data format select 0: a/d converter data format sadoh=d[11:4]; sadol=d[3:0] 1: a/d converter data format sadoh=d[11:8]; sadol=d[7:0] this bit controls the format of the 12-bit converted a/d value in the two a/d data registers. details are provided in the a/d data register section. bit 3~0 sacs3~sacs0 : a/d converter external analog channel input select 0000: an0 0001: an1 0010: an2 0011: an3 0100: an4 0101: an5 0110: an6 0111: an7 1000~1111: non-existed channel, the input will be foating if selected
rev. 1.00 74 ?a??? 0?? ?01? rev. 1.00 75 ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu c eister bit 6 5 4 3 0 name sains ? sains1 sains0 savrs1 savrs0 sacks ? sacks1 sacks0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~5 sains2~sains0 : a/d converter input signal select 000: external input external analog channel input 001: internal input internal bandgap reference voltage, v 010: internal input internal ocpao signal 011 , 100: reserved, connected to ground 101~111: external input external analog channel input care must be taken if the sains2~sains0 bits are set from 001 to 010 to select the internal analog signal to be converted. when the internal analog signal is selected to be converted, the external input pin must never be selected as the a/d input signal b y p roperly se tting t he sac s3~sacs0 b its wi th a v alue f rom 1 000 t o 1 111. otherwise, the external channel input will be connected together with the internal analog si gnal. t his wi ll re sult i n unpr edictable si tuations suc h a s a n i rreversible damage. bit 4~3 savrs1~savrs0 : a/d converter reference voltage select 00: vref pin 01: internal a/d converter power, a v 1x: vref pin these bits are used to select the a/d converter reference voltage. care must be taken if the savrs1~savrs0 bits are set to 01 to select the internal a/d converter power as the reference voltage source. when the internal a/d converter power is selected as the reference vol tage, t he vre f pi n c annot be c onfgured a s t he re ference vol tage i nput by properly confguring the corresponding pin-shared function control bits. otherwise, the external input voltage on vref pin will be connected to the internal a/d converter power. bit 2~0 sacks2~sacks0 : a/d conversion clock source select 000: f 001: f /2 010: f /4 011: f /8 100: f /16 101: f /32 110: f /64 111: f /128 these three bits are used to select the clock source for the a/d converter.
rev. 1.00 7 ? ? a ??? 0 ?? ? 01 ? rev. 1.00 77 ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu conerter eration the st art bit in the sadc0 register is used to start the ad conversion. when the microcontroller sets t his b it f rom l ow t o h igh a nd t hen l ow a gain, a n a nalog t o d igital c onversion c ycle wi ll b e initiated. the adbz bi t i n t he sadc0 re gister i s use d t o i ndicate whe ther t he a nalog t o di gital c onversion process is in progress or not. this bit will be automatically set to 1 by the microcontroller after an a/d conversion is successfully initiated. when the a/d conversion is complete, the adbz will be cleared to 0. in addition, the corresponding a/d interrupt request fag will be set in the interrupt control register , and if the interrupts are enabled, an appropriate internal interrupt signal will be generated. this a/d internal interrupt signal will direct the program flow to the associated a/d internal interrupt address for processing. if the a/d internal interrupt is disabled, the microcontroller can poll the adbz bit in the sadc0 register to check whether it has been cleared as an alternative method of detecting the end of an a/d conversion cycle. the clock source for the a/d converter , which originates from the system clock f sys , can be chosen to be either f sys or a subdivided version of f sys . the division ratio value is determined by the sacks2~sacks0 bits in the sadc1 register . although the a/d cloc k source is determined by the system clock f sys and by bits sacks2~sacks0, there are some limitations on the maximum a/d clock source speed that can be selected. as the recommended range of permissible a/d clock period, t adck , is from 0.5s to 10s, care must be taken for system clock frequencies. for example, as the system clock operates at a frequency of 8 mhz, the sacks2~sacks0 bits should not be set to 000 , 001 or 1 11. doing so will give a/d clock periods that are less than the minimum a/d clock period which m ay re sult i n i naccurate a/ d c onversion va lues. re fer t o t he fol lowing t able for e xamples, where values marked with an asteri sk * show where, depending upon the device, special care must be taken, as the values may be less than the specifed minimum a/d clock period. 1 ? hz 1s 2s 4s 8s 16s * 32s * 64s * 128s * ?? hz 500ns 1s 2s 4s 8s 16s * 32s * 64s * 4 ? hz ? 50ns * 500ns 1s 2s 4s 8s 16s * 32s * 8 ? hz 1 ? 5ns * ? 50ns * 500ns 1s 2s 4s 8s 16s * controlling t he powe r on/ off func tion of t he a/ d c onverter c ircuitry i s i mplemented usi ng t he adcen bit in the sadc0 register . this bit must be set high to power on the a/d converter . when the adcen bit is set high to power on the a/d converter internal circuitry a certain delay , as indicated in the timing diagram, must be allowed before an a/d conversion is initiated. even if no pins are selected for use as a/d inputs, if the adcen bit is high, then some power will still be consumed. in power conscious applications it is therefore recommended that the adcen is set low to reduce power consumption when the a/d converter function is not being used.
rev. 1.00 7? ?a??? 0?? ?01? rev. 1.00 77 ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu conerter eerene oltae the reference voltage supply to the a/d converter can be supplied from the positive power supply pin, a vdd, or from an external reference source supplied on pin vref . the desired selection is made using the sa vrs1 and sa vrs0 bits. when the sa vrs bit feld is set to 01, the a/d converter reference voltage will come from the a vdd pin. otherwise, if the sa vrs bit field is set to any other value except 01, the a/d converter reference voltage will come from the vref pin. as the a/d converter and ocp d/a converter external reference voltage come from the same vref pin, when the vref pin is selected as the a/d converter reference voltage pin, the ocp d/a converter reference voltage selection bit ocpvrs should be also properly confgured except the pin-shared function control bits to avoid functional abnormity . however, if the internal a/d converter power is selected as the reference voltage, the vref pin must not be confgured as the reference voltage input function for the a/d converter to avoid the internal connection between the vref pin to a/d converter power a v dd . the analog input values must not be allowed to exceed the value of the selected reference voltage, a v dd or v ref . the following table shows how to properly select reference voltage for the a/d converter or ocp d/a converter. avdd avdd 01 0 ot ? e ? s ex ? ept 10 avdd vref 01 1 01 vref avdd ot ? e ? s ex ? ept 01 0 10 vref vref ot ? e ? s ex ? ept 01 1 10 a/d conve?te? input signals all the external a/d analog channel input pins are pin-shared with the i/o pins as well as other functions. the corresponding control bits for each a/d external input pin in the p as0 and p as1 register determine w hether the input pins are s etup as a /d converter analog inputs or w hether they have other functions. if the pin is setup to be as an a/d analog channel input, the original pin functions will be disabled. in this way , pins can be changed under program control to change their function bet ween a/ d inputs and other func tions. al l pull high resi stors, whic h are set up through register programm ing, will be autom atically disconnected if the pins are setup as a/d inputs. note that it is not necessary to frst setup the a/d pin as an input in the port control register to enable the a/d input as when the pin-shared function control bits enable an a/d input, the status of the port control register will be overridden. there are two internal analog signals derived from the bandgap reference voltage or over current protection analog output signal, which can be connected to the a/d converter as the analog input signal by configuring the sains2~sains0 bits. if the external channel input is selected to be converted, the sains2~sains0 bits should be set to 000 and the sacs3~sacs0 bits can d etermine wh ich e xternal c hannel i s se lected. i f t he i nternal a nalog si gnal i s se lected t o b e converted, the sacs3~sacs0 bits must be confgured with a value from 1000 to 1 111 to switch of f the external analo g channel input. otherwise, the internal analog signal will be connected together with the external channel input. this will result in unpredictable situations.
rev. 1.00 78 ? a ??? 0 ?? ? 01 ? rev. 1.00 79 ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu 0 c30 nt inals esrition 000 ? 101~111 0000~0111 an0~an7 exte ? nal pin analog input 1000~1111 non-existed channel, input is foating. 001 1000~1111 v bg inte ? nal bandgap ? efe ? en ? e voltage 010 1000~1111 ocpao inte ? nal ove ? cu ?? ent p ? ote ? tion analog output signal 011 ? 100 1000~1111 rese ? ved ? ? onne ? ted to g ? ound. a/d conve?te? input signal sele?tion conve?sion rate and timing diag?am a com plete a/d conversi on contains two parts, dat a sampli ng and dat a conversi on. the dat a sampling which is defned as t ads takes 4 a/d clock cycles and the data conversion takes 12 a/d clock cycles. therefore a total of 16 a/d clock cycles for an external input a/d conversion which is defned as t adc are necessary. maximum single a/d conversion rate=a/d clock period / 16 the accompanying diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. after an a/d conversion process has been initiated by the application program, the microcontroller internal hardware w ill begin to carry out the conversion, d uring wh ich t ime t he p rogram c an c ontinue wi th o ther f unctions. t he t ime t aken f or t he a/d conversion is 16 t adck clock cycles where t adck is equal to the a/d clock period. adcen start adbz sacs[?:0] (sains[?:0]=000) off on off on t on?st t ads a/d sampling time t ads a/d sampling time sta?t of a/d ?onve?sion sta?t of a/d ?onve?sion sta?t of a/d ?onve?sion end of a/d ?onve?sion end of a/d ?onve?sion t adc a/d ?onve?sion time t adc a/d ?onve?sion time t adc a/d ?onve?sion time 0011b 0010b 0000b 0001b a/d ??annel swit?? a/d conve?sion timing C exte?nal c?annel input summa?y of a/d conve?sion steps the following summarises the individual steps that should be executed in order to implement an a/ d conversion process. ? step 1 select the require d a/d conversion clock by correctly programming bits sacks2~sacks0 in the sadc1 register. ? step 2 enable the a/d by setting the adcen bit in the sadc0 register to one.
rev. 1.00 78 ?a??? 0?? ?01? rev. 1.00 79 ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu ? step 3 select which signal is to be connec ted to the internal a/d converter by correctly confguring the sains2~sains0 bits. select the external channel input to be converted, go to step 4. select the internal analog signal to be converted, go to step 5. ? step 4 if the a/d input signal comes from the external channel input selecting by confguring the sains bit fel d, the corresponding pins should be confgured as a/d input functi on by confguring the relevant pin-shared function control bits. the desired analog channel then should be selected by confguring the sacs bit feld. after this step, go to step 6. ? step 5 before the a/d input signal is selected to come from the internal analog signal by confguring the sains bit feld, the corresponding external input pin must be switched to a non-existed channel input by setting the sacs3~sacs0 bits with a value from 1000 to 1 111. the desired internal analog signal then can be selected by confguring the sains bit feld. after this step, go to step 6. ? step 6 select the reference voltage source by configuring the sa vrs1~savrs0 bits in the sadc1 register. ? step 7 select a/d converter output data format by setting the adrfs bit in the sadc0 register. ? step 8 if a/d conversion interrupt is used, the interrupt control registers must be correctly confgured to ensure the a/d interrupt function is active. the master interrupt control bit, emi, and the a/d conversion interrupt control bit, ade, must both be set high in advance. ? step 9 the a/d conversion procedure can now be initialized by setting the st art bit from low to high and then low again. ? step 10 if a/ d conversi on i s i n progre ss, t he adbz fla g wi ll be se t high. aft er t he a/ d conversi on process is complete, the a dbz flag w ill go low and then the output data can be read from sadoh and sadol registers. note: when checking for the end of the conversion process, if the met hod of polling the adbz bit in the sadc0 register is used, the interrupt enable step above can be omitted. during m icrocontroller ope rations where t he a/d c onverter i s not be ing use d, t he a/d i nternal circuitry c an be swi tched of f t o re duce powe r c onsumption, by c learing bi t adce n t o 0 i n t he sadc0 regist er. when thi s happens, the int ernal a/ d converter ci rcuits wi ll not consume power irrespective of what analog voltage is applied to their input lines. if the a/d converter input lines are used as normal i/os, then care must be taken as if the input voltage is not at a valid logic level, then this may lead to some increase in power consumption.
rev. 1.00 80 ? a ??? 0 ?? ? 01 ? rev. 1.00 81 ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu conersion fntion as the device contains a 12-bit a/d converter , its full-scale converted digitised value is equal to fffh. since the full-scale analog input value is equal to the a v dd or v ref voltage, this gives a single bit analog input value of a v dd or v ref divided by 4096. 1 lsb=(av dd or v ref ) 4096 the a/d converter input voltage value can be calculated using the following equation: a/d input voltage=a/d output digital value (av dd or v ref ) 4096 the diagram shows the ideal transfer function between the analog input value and the digitised output val ue for t he a/ d conve rter. e xcept for t he di gitised ze ro val ue, t he subsequent digi tised values will change at a point 0.5 lsb below where they would change without the of fset, and the last full scale digitised value will change at a point 1.5 lsb below the a v dd or v ref level. fffh ffeh ffdh 0?h 0?h 01h 0 1 ? ? 409? 4094 4095 409? av dd o? v ref 409? analog input voltage a/d conve?sion result 1.5 lsb 0.5 lsb ideal a/d t?ansfe? fun?tion a/d conve?sion p?og?amming examples the following two programming examples illustrate how to setup and implement an a/d conversion. in the frst example, the method of polling the adbz bit in the sadc0 register is used to detect when the conversion cycle is complete, whereas in the second example, the a/d interrupt is used to determine when the conversion is complete.
rev. 1.00 80 ?a??? 0?? ?01? rev. 1.00 81 ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu ale sin an b ollin etho to etet the en o onersion clr a de ; disable adc interrupt mov a,03h mov sadc1,a ; s elect f sys /8 a s a /d cl ock set adcen mov a,03h ; s etup p as0 t o c onfgure p in a n0 mov pas0,a mov a,20h mov sadc0,a ; e nable an d c onnect a n0 c hannel t o a /d c onverter : start_conversion: clr start ; h igh p ulse o n s tart b it t o i nitiate c onversion set start ; r eset a /d clr start ; s tart a /d polling_eoc: sz adbz ; p oll t he s adc0 r egister a dbz b it t o d etect e nd o f a /d c onversion jmp polling_eoc ; c ontinue p olling mov a,sadol ; re ad l ow b yte c onversion re sult v alue mov sadol_buffer,a ; s ave r esult t o us er d efned r egister mov a,sadoh ; re ad h igh b yte c onversion re sult v alue mov sadoh_buffer,a ; s ave r esult t o us er d efned r egister : : jmp start_conversion ; s tart n ext a/ d c onversion clr a de ; disable adc interrupt mov a,03h mov sadc1,a ; s elect f sys /8 a s a /d cl ock set adcen mov a,03h ; s etup p as0 t o c onfgure p in a n0 mov pas0,a mov a,20h mov sadc0,a ; e nable an d c onnect a n0 c hannel t o a /d c onverter start_conversion: clr start ; h igh p ulse o n st art b it t o i nitiate c onversion set start ; r eset a /d clr start ; s tart a /d clr adf ; c lear a dc i nterrupt re quest f ag set a de ; enable adc interrupt set emi ; e nable gl obal i nterrupt : : ; adc interrupt service routine adc_isr: mov acc_stack,a ; s ave a cc t o u ser d efned m emory mov a,status mov status_stack,a ; s ave st atus t o us er d efned m emory : : mov a,sadol ; re ad l ow b yte c onversion re sult v alue mov sadol_buffer,a ; s ave r esult t o us er d efned r egister mov a,sadoh ; re ad h igh b yte c onversion re sult v alue mov sadoh_buffer,a ; s ave r esult t o us er d efned r egister : : exit_int_isr: mov a,status_stack mov status,a ; restore s tatus f rom u ser d efned m emory mov a,acc_stack ; r estore a cc fr om u ser d efned m emory reti
rev. 1.00 8 ? ? a ??? 0 ?? ? 01 ? rev. 1.00 8? ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu er crrent protetion the device includes an over current protection function which provides a protection mechanism for a pplications. t o pre vent t he ba ttery c harge or l oad c urrent from e xceeding a spec ific l evel, the current on the ocp pin is converted to a relevant voltage level according to the current value using the o cp operational amplif er. it is then compared w ith a reference voltage generated by an 8-bit d/a convert er. when an over current event occurs, an ocp interrupt will be generated if the corresponding interrupt control is enabled. ocpi ocpao (to a/d inte?nal input) ocpint ocpchy s4 - + g[?:0] r? opa + - 8-bit dac ocpcout deboun?e ocpo ocpdeb[?:0] r1 (r1 = 4k) ocpen[1:0] ? u x ocpda[7:0] ocpvrs f sys s0 s1 s? s? c?p av dd v ref ove? cu??ent p?ote?tion ci??uit ove? cu??ent p?ote?tion ope?ation t he i llustrated oc p c ircuit i s use d t o pre vent t he i nput c urrent from e xceeding a re ference l evel. t he current on the ocp pin is converted to a voltage and then amplifed by the ocp operational amplifer with a programmable gain from 1 to 50 selected by the g2~g0 bits in the ocpc1 register . t his is known as a programmable gain amplifier or pga. t his pga can also be configured to operate in the non-inverting, inverting or input of fset calibration mode determined by the ocpen1 and ocpen0 bits in the ocpc0 register . a fter the current is converted and amplifed to a specifc voltage level, it will be compared with a reference voltage provided by an 8-bit dac. the 8 -bit dac power can be a v dd or v ref , selected by the ocpvrs bit in the ocpc0 register . t he comparator output, ocpcout , will frst be fltered with a certain de-bounce time period selected by t he ocpde b2~ocpdeb0 bi ts i n t he ocpc1 re gister. t hen a fl tered ocp di gital c omparator output, ocpo, is obtained to indica te whether an over current conditi on occurs or not. t he ocpo bit will be set to 1 if an over current condition occurs. o therwise, the ocpo bit is zero. once an over current event occurs, i.e., the converted voltage of the o c p input current is greater than the reference voltage, the corresponding interrupt will be generated if the relevant interrupt control bit is enabled .
rev. 1.00 8? ?a??? 0?? ?01? rev. 1.00 8 ? ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu er crrent protetion control eisters overall operation of the over current protection is controlled using several registers. one register is used to provide the reference voltag es for the over current protection circuit. there are two registers used to cancel out the operational amplifer and comparator input offset. the remaining two registers are control registers which control the ocp function, d/a converter reference voltage select, pga gain select, comparator de-bounce time together with the hysteresis function. ocpc0 ocpen1 ocpen0 ocpvrs ocpchy ocpo ocpc1 g ? g1 g0 ocpdeb ? ocpdeb1 ocpdeb0 ocpda d7 d ? d5 d4 d ? d ? d1 d0 ocpocal ocpoof ? ocporsp ocpoof5 ocpoof4 ocpoof ? ocpoof ? ocpoof1 ocpoof0 ocpccal ocpcout ocpcof ? ocpcrsp ocpcof4 ocpcof ? ocpcof ? ocpcof1 ocpcof0 ocp registe? list ocpc0 registe? bit 7 ? 5 4 ? ? 1 0 name ocpen1 ocpen0 ocpvrs ocpchy ocpo r/w r/w r/w r/w r/w r por 0 0 0 0 0 bit 7~6 ocpen1~ocpen0 : ocp function operating mode selection 00: ocp function is disabled, s1and s3 on, s0 and s2 off 01: non-inverting mode, s0 and s3 on, s1 and s2 off 10: inverting mode, s1 and s2 on, s0 and s3 off 11: calibration mode, s1 and s3 on, s0 and s2 off bit 5 ocpvrs : ocp dac reference voltage selection 0: from a v 1: from v ref bit 4 ocpchy : ocp comparator hysteresis function control 0: disable 1: enable bit 3~1 unimplemented, read as 0 bit 0 ocpo : ocp digital output bit 0: the monitored source current is not over 1: the monitored source current is over
rev. 1.00 84 ? a ??? 0 ?? ? 01 ? rev. 1.00 85 ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu cpc eister bit 6 5 4 3 0 name g ? g1 g0 ocpdeb ? ocpdeb1 ocpdeb0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5~3 g2~g0 : pga r2/r1 ratio selection 000: unity gain buffer (non-inverting mode) or r2/r1=1(inverting mode) 001: r2/r1=5 010: r2/r1=10 011: r2/r1=15 100: r2/r1=20 101: r2/r1=30 110: r2/r1=40 111: r2/r1=50 these bits are used to select the r2/r1 ratio to obtain various gain values for inverting and non-inverting mode. the calculating formula of the pga gain for the inverting and non-inverting mode is described in the input v oltage range section. bit 2~0 ocpdeb2~ocpdeb0 : ocp output flter debounce time selection 000: bypass, without debounce 001: (1~2) t deb 010: (3~4) t deb 011: (7~8) t deb 100: (15~16) t deb 101: (31~32) t deb 110: (63~64) t deb 111: (127~128) t deb note: t deb =1/f name d7 d ? d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : ocp dac output voltage control bits ocp dac output=(dac reference voltage/256) d[7:0]
rev. 1.00 84 ?a??? 0?? ?01? rev. 1.00 85 ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu cpc eister bit 6 5 4 3 0 name ocpoof ? ocporsp ocpoof5 ocpoof4 ocpoof ? ocpoof ? ocpoof1 ocpoof0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 1 0 0 0 0 0 bit 7 ocpoofm : ocp operational amplifer input offset calibration mode enable control 0: input offset calibration mode disabled 1: input offset calibration mode enabled this bit is used to control the ocp operational amplifier input of fset calibration function. t he oc pen1 a nd oc pen0 b its m ust f irst b e se t t o 11 a nd t hen t he ocpoofm bit must be set to 1 followed by the ocpcofm bit being setting to 0, then the operational amplifier input of fset calibration mode w ill be enabled. refer to the operationa l amplifer input of fset calibration section for the detailed of fset calibration procedures. bit 6 ocporsp : ocp operational amplifer input offset v oltage calibration reference selection 0: select negative input as the reference input 1: select positive input as the reference input bit 5~0 ocpoof5~ocpoof0 : ocp operational amplifer input offset v oltage calibration value this 6-bit feld is used to perform the operational amplifer input of fset calibration operation and the value for the ocp operational amplifer input of fset calibration can be restored i nto this bit feld. more detailed information is described in the operational amplifer input offset calibration section. name ocpcout ocpcof ? ocpcrsp ocpcof4 ocpcof ? ocpcof ? ocpcof1 ocpcof0 r/w r r/w r/w r/w r/w r/w r/w r/w por 0 0 0 1 0 0 0 0 bit 7 ocpcout : ocp comparator output, positive logic (read only) 0: positive input voltage < negative input voltage 1: positive input voltage > negative input voltage this bit is used to indicate whether the positive input voltage is greater than the negative input voltage when the ocp operates in the input of fset calib ration mode. if the ocpcout is set to 1, the positive input voltage is greater than the negative input voltage. otherwise, the positive input voltage is less than the negative input voltage. bit 6 ocpcofm : ocp comparator input offset calibration mode enable control 0: input offset calibration mode disabled 1: input offset calibration mode enabled this bit is used to control the ocp comparator input of fset calibration function. the ocpen1 and ocpen0 bits must frst be set to 1 1 and then the ocpcofm bit must be se t t o 1 fol lowed by t he ocpoofm bi t be ing se tting t o 0, t hen t he c omparator input of fset calibration mode w ill be enabled. refer to the comparator input o ffset calibration section for the detailed offset calibration procedures. bit 5 ocpcrsp : ocp comparator input offset calibration reference input select 0: select negative input as the reference input 1: select positive input as the reference input bit 4~0 ocpcof4~ocpcof0 : ocp comparator input offset calibration value this 5-bit feld is used to perform the comparator input of fset calibration operation and t he val ue for t he ocp com parator i nput of fset c alibration ca n be rest ored i nto this bit feld. more detailed informa tion is described in the comparat or input of fset calibration section.
rev. 1.00 8 ? ? a ??? 0 ?? ? 01 ? rev. 1.00 87 ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu nt oltae ane together with dif ferent pga operating modes, the input voltage on the ocp pin can be positive or negative for flexible operation. the pga output for the positive or negative input voltage is calculated based on different formulas and described by the following. ? for input voltages v in > 0, the pga operates in the non-inverting mode and the pga output is obtained using the formula below: v out = (1 + r2 r1 ) v in ? when the pga operates in the non-inverting mode by setting the ocpen[1:0] to 01 with unity gain select by setting the g[2:0] to 000, the pga will act as a unit-gain buf fer whose output is equal to v in . v out = v in ? for input voltages 0 >v in >-0.4v , the pga operates in the inverting mode and the pga output is obtaine d using the formula below . note that if the input voltage is negative, it cannot be lower than -0.4v which will result in current leakage. v out = ? r2 r1 v in the ocp circuit has 4 operating modes controlled by ocpen[1:0], one of them is calibration mode. in calibration mode, operational amplifer and comparator offset can be calibrated. operational amplifer input offset calibration step 1. set ocpen[1:0]=1 1, ocpoofm=1 and ocpcofm=0, the ocp will operate in the operational amplifer input offset calibration mode. step 2. set ocpoof[5:0]=000000 and then read the ocpcout bit. step 3. increase the ocpoof[5:0] value by 1 and then read the ocpcout bit. if the ocpcout bit state has not changed, then repeat step 3 until the ocpcout bit state has changed. if the ocpcout bit state has changed, record the ocpoof value as v oos1 and then go to step 4. step 4. set ocpoof[5:0]=111111 and read the ocpcout bit. step 5. decrease the ocpoof[5:0] value by 1 and then read the ocpcout bit. if the ocpcout bit state has not changed, then repeat step 5 until the ocpcout bit state has changed. if the ocpcout bit state has changed, record the ocpoof value as v oos2 and then go to step 6. step 6. restore the operational amplifer input of fset calibration value v oos into the ocpoof[5:0] bit feld. the offset calibration procedure is now fnished. where v oos = v oos1 + v oos2 2
rev. 1.00 8? ?a??? 0?? ?01? rev. 1.00 87 ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu coarator nt set caliration step 1 . se t oc pen[1:0]=11, oc pcofm=1 a nd oc poofm=0, t he oc p wi ll n ow o perate i n t he comparator i nput o ffset c alibration m ode. s4 i s o n ( s4 i s u sed f or c alibration m ode, i n normal mode operation, it is off). step 2. set ocpcof[4:0]=00000 and read the ocpcout bit. step 3. increase the ocpcof[4:0] value by 1 and then read the ocpcout bit. if the ocpcout bit state has not changed, then repeat step 3 until the ocpcout bit state has changed. if the ocpcout bit state has changed, record the ocpcof value as v cos1 and then go to step 4. step 4. set ocpcof[4:0]=11111 and then read the ocpcout bit. step 5. decrease the ocpcof[4:0] value by 1 and then read the ocpcout bit. if the ocpcout bit state has not changed, then repeat step 5 until the ocpcout bit state has changed. if the ocpcout bit state has changed, record the ocpcof value as v cos2 and then go to step 6. step 6. restore the comparator input of fset calibration value v cos into the ocpcof[4:0] bit feld. the offset calibration procedure is now fnished. where v cos = v cos1 + v cos2 2 the device contai ns a high voltage driver with level shift functions, which can be used to drive the external power mos. hvo hv output control en oe* vcc vdd ptp0 m u x hvo vcc hvods vcc vdd hvooe d* hvop0en ocpo hvop1en int0 hvop2en hvop2 hvop3en hvop3 p* hvopen level shift level shift h/w protection control note: 1. * is the circuit node name and not the special function register bit. 2. ptp0 acted as the control signal output high /low (d) source.
rev. 1.00 88 ? a ??? 0 ?? ? 01 ? rev. 1.00 89 ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu fntional esrition the high voltage output on the hvo pin is used to drive the external power mos by the hvo bit high/low or using ptp0 output to control power mos loads, the control methods can be selected by the hvods bit. there is a protection mechanism provided for high voltage output. ? if hvope n=0, wh ether t he hvo p in i s i n a f loating st atus o r n ormally o utputs a s a bove described methods will be determined by the hvooe bit. ? if hvopen=1, when the control signal p trigger from low to high occurs, frst the hvo and hvods bits will be forced to be cleared to zero, the purpose is as follows. ? when oe=1, the hvo pin output status is low. ? when oe=0, the hvo pin output status is foating, where the oe value is decided by the hvooe bit. then the action of the hvoc register is determined by software. ? if hvopen=1, but the control signal p trigger does not occur , then the hvo and hvods bits will not be affected. these two registers are used to control the overall operation of high voltage output. name hvopen hvooe hvods hvo r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~4 unimplemented, read as 0 bit 3 hvopen : hvo pin h/w protection enable control 0: disable 1: enable bit 2 hvooe : hvo pin output enable control 0: output disable 1: output enable bit 1 hvods : hvo pin output data select 0: output decide by hvo bit 1: output decide by ptp0 bit 0 hvo : hvo pin output control 0: output low 1: output high note: as the hvooe and hvo bits are in the same register , when the hvoc register is confgured, there is a system clock f delay provided between the hvo pin output enable and data signals by hardware, to solve the problem due to these two signals are too closed.
rev. 1.00 88 ?a??? 0?? ?01? rev. 1.00 89 ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu hpc eister bit 6 5 4 3 0 name hvop ? en hvop ? en hvop1en hvop0en r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~4 unimplemented, read as 0 bit 3 hvop3en : hvop3 h/w protection control 0: disable 1: enable bit 2 hvop2en : hvop2 h/w protection control 0: disable 1: enable bit 1 hvop1en : int0 h/w protection control 0: disable 1: enable bit 0 hvop0en : ocpo h/w protection control 0: disable 1: enable the i 2 c interface is used to communicate with external peripheral devices such as sensors, eeprom m emory e tc. or iginally d eveloped b y ph ilips, i t i s a t wo l ine l ow sp eed se rial i nterface for synchronous serial data transfer . the advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. devi?e slave devi?e ?aste? devi?e slave vdd sda scl i ? c ?aste?/slave bus conne?tion i ? c inte?fa?e ope?ation the i 2 c serial interface is a two line interf ace, a serial data line, sda, and serial clock line, scl. as many devices may be connected together on the same bus, their outputs are both open drain types. for this reason it is necessary that external pull-high resistors are connected to these outputs. note that no chip select line exists, as each device on the i 2 c bus is identifed by a unique address which will be transmitted and received on the i 2 c bus. when two device s communicate with each other on the bidirectional i 2 c bus, one is known as the master de vice a nd one a s t he sl ave de vice. bot h m aster a nd sl ave c an t ransmit a nd re ceive da ta, however, i t i s t he m aster de vice t hat ha s ove rall c ontrol of t he bus. for t his de vice, wh ich onl y operates in slave mode, there are two methods of transferring data on the i 2 c bus, the slave transmit mode and the slave receive mode.
rev. 1.00 90 ? a ??? 0 ?? ? 01 ? rev. 1.00 91 ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu s?ift registe? t?ansmit/ re?eive cont?ol unit f sys f sub data bus i ? c add?ess registe? (iica) i ? c data registe? (iicd) add?ess compa?ato? read/w?ite slave srw dete?t sta?t o? stop hbb time-out cont?ol iictof add?ess ?at?? C haas i ? c inte??upt deboun?e ci??uit?y scl pin ? u x txak data out ?sb iictoen add?ess ?at?? iicdeb[1:0] sda pin data in ?sb di?e?tion cont?ol htx 8-bit data t?ansfe? complete C hcf i ? c blo?k diag?am start signal f?om ?aste? send slave add?ess and r/w bit f?om ?aste? a?knowledge f?om slave send data byte f?om ?aste? a?knowledge f?om slave stop signal f?om ?aste? the iicdeb 1 and iicdeb 0 bits determine the debounce time of the i 2 c interface. this uses the system clock to in ef fect add a debounce time to the external clock to reduce the possibility of glitches on the clock line causing erroneous operation. the debounce time, if selected, can be chosen to be either 2 or 4 sys tem clocks. t o achieve the required i 2 c data trans fer speed, there exists a relationship between the system clock, f sys , and the i 2 c debounce time. for either the i 2 c standard or fast mode operation, users must take care of the selected system clock frequency and the confgured debounce time to match the criterion shown in the following table. no deboun ? e f sys > ? ? hz f sys > 5 ? hz ? system ? lo ? k deboun ? e f sys > 4 ? hz f sys > 10 ? hz 4 system ? lo ? k deboun ? e f sys > 8 ? hz f sys > ? 0 ? hz i ? c ?inimum f sys f?equen?y
rev. 1.00 90 ?a??? 0?? ?01? rev. 1.00 91 ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu c eisters there a re three c ontrol r egisters a ssociated wi th t he i 2 c b us, i icc0, i icc1 a nd i ictoc , a nd o ne slave address register, iica, together with one data register, iicd. iicc0 iicdeb1 iicdeb0 iicen iicc1 hcf haas hbb htx txak srw ia ? wu rxak iicd d7 d ? d5 d4 d ? d ? d1 d0 iica a ? a5 a4 a ? a ? a1 a0 iictoc iictoen iictof iictos5 iictos4 iictos ? iictos ? iictos1 iictos0 i ? c registe?s list iicd registe? the iicd register is used to store the data being transmitted and receiv ed on the i 2 c bus. before the microcontroller writes data to the i 2 c bus, the actual data to be transmitted must be placed in the iicd register . after the data is received from the i 2 c bus, the microcontroller can read it from the iicd register . any transmission or reception of data from the i 2 c bus must be made via the iicd register. name d7 d ? d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x x: unknown bit 7~0 d7~d0 : i 2 c data buffer bit 7~bit 0 the iica register is the location where the 7-bit slave address of the slave device is stored. bits 7~1 of t he i ica r egister d efne t he d evice sl ave a ddress. b it 0 i s n ot d efned. when a m aster d evice, which is connected to the i 2 c bus, sends out an address, which matches the slave address in the iica register, the slave device will be selected. name a ? a5 a4 a ? a ? a1 a0 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7~1 a6~a0 : i 2 c slave address a6~a0 is the i 2 c slave address bit 6 ~ bit 0. bit 0 unimplemented, read as 0
rev. 1.00 9 ? ? a ??? 0 ?? ? 01 ? rev. 1.00 9? ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu c control eisters there are two control registers for the i 2 c interface , iicc0 and iicc1. the re gister iicc0 is used to control the enable/disable function and to set the data transmission clock frequency . the iicc1 register contains the relevant fags which are used to indicate the i 2 c communication status . a nother register, iict oc, is used to control the i 2 c time-out function and described in the corresponding section. ? name iicdeb1 iicdeb0 iicen r/w r/w r/w r/w por 0 0 0 bit 7~4 unimplemented, read as 0 bit 3~2 iicdeb1~iicdeb0 : i 2 c debounce t ime selection 00: no debounce 01: 2 system clock debounce 10: 4 system clock debounce 11: 4 system clock debounce bit 1 iicen : i 2 c enable 0: disable 1: enable the bit is the overall on/off control for the i 2 c interface. when the en bit is cleared to zero to disable the i 2 c interface, the sda and scl lines will lose their i 2 c function and t he i 2 c o perating c urrent wi ll b e r educed t o a m inimum v alue. w hen t he b it i s high the i 2 c interface is enabled. if the en bit changes from low to high, the contents of the i 2 c control bits such as htx and txak will remain at the previous settings and should therefore be frst initialised by the application program while the relevant i 2 c fags such as hcf, haas, hbb, srw and rxak will be set to their default states. bit 0 unimplemented, read as 0 ? name hcf haas hbb htx txak srw ia ? wu rxak r/w r r r r/w r/w r r/w r por 1 0 0 0 0 0 0 1 bit 7 hcf : i 2 c bus data transfer completion fag 0: data is being transferred 1: completion of an 8-bit data transfer the hcf flag is the data transfer flag. this flag will be zero when data is being transferred. upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated. below is an example of the fow of a two-byte i 2 c data transfer. first, i 2 c slave device receive a start signal from i 2 c master and then hcf bit is automatically cleared to zero. second, i 2 c slave device finish receiving the 1st data byte and then hcf bit is automatically set to one. third, user read the 1st data byte from iicd register by the application program and then hcf bit is automatically cleared to zero. fourth, i 2 c slave device finish receiving the 2nd data byte and then hcf bit is automatically set to one and so on. finally, i 2 c slave device receive a stop signal from i 2 c master and then hcf bit is automatically set to one.
rev. 1.00 9? ?a??? 0?? ?01? rev. 1.00 9 ? ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu bit 6 : i 2 c bus address match fag 0: not address match 1: address match the haas fa g i s t he a ddress m atch fa g. t his fa g i s use d t o de termine i f t he sl ave device address is the same as the master transmit address. if the addresses match then this bit will be high, if there is no match then the fag will be low. bit 5 : i 2 c bus busy fag 0: i 2 c bus is not busy 1: i 2 c bus is busy the hbb flag is the i 2 c busy flag. this flag will be 1 when the i 2 c bus is busy which will occur when a st art signal is detected. the fag will be set to 0 when the bus is free which will occur when a stop signal is detected. bit 4 : select i 2 c slave device is transmitter or receiver 0: slave device is the receiver 1: slave device is the transmitter bit 3 : i 2 c bus transmit acknowledge fag 0: slave send acknowledge fag 1: slave do not send acknowledge fag the txak bit is the transmit acknowledge fag. after the slave device receipt of 8-bits of data, this bit will be transmitted to the bus on the 9th clock from the slave device. the slave device must always set txak bit to "0" before further data is received. bit 2 : i 2 c slave read/write fag 0: slave device should be in receive mode 1: slave device should be in transmit mode the sr w f lag i s t he i 2 c sl ave r ead/write f lag. t his f lag d etermines wh ether the master device wishes to transmit or receive data from the i 2 c bus. when the transmitted address and slave address is match, that is when the haas fag is set high, the slave device will check the sr w fag to determine whether it should be in transmit mode or receive mode. if the sr w fag is high, the master is requesting to read data from the bus, so the slave device should be in transmit mode. when the sr w flag is zero, the master will write data to the bus, therefore the slave device should be in receive mode to read this data. bit 1 : i 2 c address match control 0: disable 1: enable this bit should be set to 1 to enabl e the i 2 c address match wake up from the sleep or idle mode. if the iamwu bit has been set before entering either the sleep or idle mode to enable the i 2 c address match wake up, then this bit must be cleared by the application program after wake-up to ensure correction device operation. bit 0 : i 2 c bus receive acknowledge fag 0: slave receive acknowledge fag 1: slave do not receive acknowledge fag the r xak fl ag i s t he r eceiver a cknowledge f lag. w hen t he r xak f lag i s 0, i t means that a acknowledge signal has been received at the 9th clock, after 8 bits of data have been transmitted. when the slave device in the transmit mode, the slave device checks the rxak fag to determine if the master receiver wishes to receive the next byte. t he sl ave t ransmitter wi ll t herefore c ontinue se nding out da ta unt il t he rxak fag is 1. when this occurs, the slave transmitter will release the sda line to allow the master to send a stop signal to release the i 2 c bus.
rev. 1.00 94 ? a ??? 0 ?? ? 01 ? rev. 1.00 95 ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu c bs coniation communication on the i 2 c bus requires four separate steps, a st art signal, a slave device address transmission, a data transmission and finally a st op signal. when a st art signal is placed on the i 2 c bus, all devices on the bus will receive this signal and be notifed of the imminent arrival of data on the bus. the frst seven bits of the data will be the slave address with the frst bit being the msb. if the address of the slave device matches that of the transmitted address, the haas bit in the iicc1 register will be set and an i 2 c interrupt will be generated. after entering the interrupt service routine, the slave device must frst check the condition of the haas and iict of bits to determine whether the interrupt source originates from an address match or from the completion of an 8-bit data t ransfer c ompletion o r i 2 c b us t ime-out o ccurrence . du ring a d ata t ransfer, n ote t hat a fter t he 7-bit slave address has been transmitted, the following bit, which is the 8th bit, is the read/write bit whose value will be placed in the sr w bit. this bit will be checked by the slave device to determine whether to go into transmit or recei ve mode. before any transfer of data to or from the i 2 c bus, the microcontroller must initialise the bus, the following are steps to achieve this: ? step 1 set iicen bit in the iicc0 register to 1 to enable the i 2 c bus. ? step 2 write the slave address of the device to the i 2 c bus address register iica. ? step 3 set the iice interrupt enable bit of the interrupt control register to enable the i 2 c interrupt. sta?t set iicen w?ite slave add?ess to iica i ? c bus inte??upt=? clr iice poll iicf to de?ide w?en to go to i ? c bus isr set iice wait fo? inte??upt go to ?ain p?og?am go to ?ain p?og?am yes no i ? c bus initialisation flow c?a?t
rev. 1.00 94 ?a??? 0?? ?01? rev. 1.00 95 ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu c bs tart inal the st art signal can only be generated by the master device connec ted to the i 2 c bus and not by the slave device. this st art signal will be detected by all devices connected to the i 2 c bus. when detected, this indicates that the i 2 c bus is busy and therefore the hbb bit will be set. a st art condition occurs when a high to low transition on the sda line takes place when the scl line remains high. the t ransmission o f a st art si gnal b y t he m aster wi ll b e d etected b y a ll d evices o n t he i 2 c b us. to determine which slave device the master wishes to communicate with, the address of the slave device will be sent out immediately following the st art signal. all slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. if the address sent out by the maste r matche s the internal address of the microcontroller slave device, then an internal i 2 c bus interrupt signal wil l be generat ed. the next bit fol lowing the address, which is the 8th bit, defnes the read/write status and will be saved to the sr w bit of the iicc1 register . the slave device will then transmit an acknowledge bit, which is a low level, as the 9th bit. the slave device will also set the status fag haas when the addresses match. as a n i 2 c bus i nterrupt c an c ome fro m three sourc es, whe n t he progra m e nters t he i nterrupt subroutine, the haas and iict of bits should be examined to see whether the interrupt source has come from a matching slave address or from the completion of a data byte transfer or i 2 c time-out. when a slave address is matched, the device must be placed in either the transmit mode and then write data to the iicd register , or in the receive mode where it must implement a dummy read from the iicd register to release the scl line. the sr w bit in the iicc1 register defnes whether the master device wishes to read data from the i 2 c bus or write data to the i 2 c bus. the slave device should examine this bit to determine if it is to be a transmitter or a receiver . if the sr w fag is 1 then this indicates that the master device wishes to read data from the i 2 c bus, therefore the slave device must be setup to send data to the i 2 c bus as a transmitter . if the sr w fag is 0 then this indicates that the master wishes to send data to the i 2 c bus, therefore the slave device must be setup to read data from the i 2 c bus as a receiver. after the mas ter has trans mitted a calling addres s, any s lave device on the i 2 c bus , w hose own internal address matches the calling address, must generate an acknowledge signal. the acknowledge signal will inform the master that a slave device has accepted its calling address. if no acknowledge signal is received by the master then a st op signal must be transmitted by the master to end the communication. when the haas fag is high, the addresses have matched and the slave device m ust c heck t he sr w fa g t o de termine i f i t i s t o be a t ransmitter or a re ceiver. if t he sr w fag is high, the slave device should be setup to be a transmitter so the htx bit in the iicc1 register should be set to 1. if the sr w fag is low , then the microcontroller slave device should be setup as a receiver and the htx bit in the iicc1 register should be set to 0.
rev. 1.00 9 ? ? a ??? 0 ?? ? 01 ? rev. 1.00 97 ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu c bs ata an nowlee inal the transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged receipt o f i ts sl ave a ddress. t he o rder o f se rial b it t ransmission i s t he msb fr st a nd t he l sb l ast. after receipt of 8-bits of data, the receiver must transmit an acknowle dge signal, level 0, before it can receive the next data byte. if the slave transmitter does not recei ve an acknowledge bit signal from the master receiver , then the slave transmitter will release the sda line to allow the master to send a st op signal to release the i 2 c bus. the corresponding data will be stored in the iicd register. if setup as a transmitter , the slave device must frst write the data to be transmitted into the iicd register . if setup as a receiver , the slave device must read the transmitted data from the iicd register. when the slave receiver receives the data byte, it must generate an acknowledge bit, known as txak, on the 9th clock. the slave device, which is setup as a transmi tter will check the rxak bit in the iicc1 register to determine if it is to send another data byte, if not then it will release the sda line and await the receipt of a stop signal from the master. sta?t scl sda scl sda 1 s=sta?t (1 bit) sa=slave add?ess (7 bits) sr=srw bit (1 bit) ?=slave devi?e send a?knowledge bit (1 bit) d=data (8 bits) a=ack (rxak bit fo? t?ansmitte?? txak bit fo? ?e?eive?? 1 bit) p=stop (1 bit) 0 ack slave add?ess srw stop data ack 1101010 10010100 s sa sr ? d a d a s sa sr ? d a d a p note: *when a slave address is matched, the device must be placed in either the transmit mode and then write data to the iicd register , or in the receive mode where it must implement a dummy read from the iicd register to release the i 2 c scl line.
rev. 1.00 9? ?a??? 0?? ?01? rev. 1.00 97 ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu sta?t iictof=1? set iictoen clr iictof reti haas=1? htx=1? srw=1? read f?om iicd to ?elease scl line reti rxak=1? w?ite data to iicd to ?elease scl line clr htx clr txak dummy ?ead f?om iicd to ?elease scl line reti reti set htx w?ite data to iicd to ?elease scl line reti clr htx clr txak dummy ?ead f?om iicd to ?elease scl line reti yes no no yes yes no yes no no yes i ? c bus isr flow c?a?t i ? c time-out cont?ol in order to reduce the problem of i 2 c lockup due to reception of erroneous clock sources, a time-out function is provided. if the clock source to the i 2 c is not received for a while, then the i 2 c circuitry and registers will be reset after a certain time-out period . the time-out counter starts counting on an i 2 c bus st art & address match condition, and is cleared by an scl falling edge. before the next scl falling edge arrives, if the time elapsed is greater than the time-out setup by the iict oc register, then a tim e-out condition will occur . the time-out function will stop when an i 2 c st op condition occurs. sta?t scl sda scl sda 1 0 ack slave add?ess srw stop 1101010 10010100 i ? c time-out ?ounte? sta?t i ? c time-out ?ounte? ?eset on scl negative t?ansition i ? c time-out
rev. 1.00 98 ? a ??? 0 ?? ? 01 ? rev. 1.00 99 ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu when an i 2 c time -out counte r overfow occurs, the counter will stop and the iict oen bit will be cleared t o z ero a nd t he i ictof bit wi ll b e se t h igh t o i ndicate t hat a t ime-out c ondition h as occurred. the time-out condition will also generate an interrupt which uses the i 2 c interrupt vector . when an 2 c time-out occurs, the i 2 c internal circuitry will be reset and the registers will be reset into the following condition: register after i 2 c time-out iicd ? iica ? iicc0 no ?? ange iicc1 reset to por ? ondition i 2 c registers a fter time-out the iict of fag can be cleared by the application program. there are 64 time-out periods which can be selected using bits in the iictoc register. the time-out time is given by the formula: ((1~64) 32) / f this gives a range of about 1ms to 64ms. iictoc register bit 7 6 5 4 3 2 1 0 name iictoen iictof iictos5 iictos4 iictos ? iictos ? iictos1 iictos0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 : i 2 c t ime-out control 0: disable 1: enable bit 6 : t ime-out fag (set by time-out and clear by software) 0: no time-out 1: t ime-out occurred bit 5~0 : t ime-out defnition 2 c time-out clock source is f /32. 2 c time-out time is given by: (iictos [5 0]+1) (32/f ) interrupts interrupts are an important part of any microcontroller s ystem. when an external event or an internal function such as a t imer module or an a/d converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. the device contains several external interrupt and internal interrupts functions. the external interrupts are generated by the action of the external int0~int1 pins, while the internal interrupts are generated by various internal functions such as the tms, t ime base, lvd, eeprom and the a/d converter. interrupt registers overall interrupt control, w hich bas ically means the s etting of reques t flags w hen certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is cont rolled by a se ries of regi sters, l ocated i n t he spe cial purpose dat a me mory. the frst i s t he intc0~intc2 registers which setup the primary interrupts, the second is the mfi0~mfi1 registers which setup the multi-function interrupts. finally there is an integ register to setup the external interrupt trigger edge type.
rev. 1.00 98 ?a??? 0?? ?01? rev. 1.00 99 ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu each regist er contai ns a number of enable bit s to enable or disa ble indivi dual regist ers as wel l as interrupt flags to indicate the presence of an interrupt request. the naming convention of these follows a specifc pattern. first is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an e for enable/disable bit or f for request fag. global e ? i intn pin intne intnf n=0~1 ? ulti-fun ? tion ? fne ? fnf n=0~1 a/d conve ? te ? ade adf time base tbne tbnf n=0~1 lvd lve lvf eepro ? dee def i ? c iice iicf ove ? cu ?? ent p ? ote ? tion ocpe ocpf pt ? pt ? npe pt ? npf n=0~1 pt ? nae pt ? naf inte??upt registe? bit naming conventions registe? name bit 7 ? 5 4 ? ? 1 0 integ int1s1 int1s0 int0s1 int0s0 intc0 int1f ocpf int0f int1e ocpe int0e e ? i intc1 tb1f tb0f ? f1f ? f0f tb1e tb0e ? f1e ? f0e intc ? def lvf adf iicf dee lve ade iice ? fi0 pt ? 0af pt ? 0pf pt ? 0ae pt ? 0pe ? fi1 pt ? 1af pt ? 1pf pt ? 1ae pt ? 1pe inte??upt registe? contents integ registe? bit 7 ? 5 4 ? ? 1 0 name int1s1 int1s0 int0s1 int0s0 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~4 unimplemented, read as 0 bit 3~2 int1s1~int1s0 : interrupt edge control for int1 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges bit 1~0 int0s1~int0s0 : interrupt edge control for int0 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges
rev. 1.00 100 ? a ??? 0 ?? ? 01 ? rev. 1.00 101 ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu tc0 eister bit 6 5 4 3 0 name int1f ocpf int0f int1e ocpe int0e e ? i r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as 0 bit 6 int1f : int1 interrupt request fag 0: no request 1: interrupt request bit 5 ocpf : ocp interrupt request fag 0: no request 1: interrupt request bit 4 int0f : int0 interrupt request fag 0: no request 1: interrupt request bit 3 int1e : int1 interrupt control 0: disable 1: enable bit 2 ocpe : ocp interrupt control 0: disable 1: enable bit 1 int0e : int0 interrupt control 0: disable 1: enable bit 0 emi : global interrupt control 0: disable 1: enable
rev. 1.00 100 ?a??? 0?? ?01? rev. 1.00 101 ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu tc eister bit 6 5 4 3 0 name tb1f tb0f ? f1f ? f0f tb1e tb0e ? f1e ? f0e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 tb1f : t ime base 1 interrupt request fag 0: no request 1: interrupt request bit 6 tb0f : t ime base 0 interrupt request fag 0: no request 1: interrupt request bit 5 mf1f : multi-function interrupt 1 request fag 0: no request 1: interrupt request bit 4 mf0f : multi-function interrupt 0 request fag 0: no request 1: interrupt request bit 3 tb1e : t ime base 1 interrupt control 0: disable 1: enable bit 2 tb0e : t ime base 0 interrupt control 0: disable 1: enable bit 1 mf1e : multi-function interrupt 1 control 0: disable 1: enable bit 0 mf0e : multi-function interrupt 0 control 0: disable 1: enable
rev. 1.00 10 ? ? a ??? 0 ?? ? 01 ? rev. 1.00 10? ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu tc eister bit 6 5 4 3 0 name def lvf adf iicf dee lve ade iice r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 def : data eeprom interrupt request fag 0: no request 1: interrupt request bit 6 lvf : lvd interrupt request fag 0: no request 1: interrupt request bit 5 adf : a/d converter interrupt request fag 0: no request 1: interrupt request bit 4 iicf : i 2 c interrupt request fag 0: no request 1: interrupt request bit 3 dee : data eeprom interrupt control 0: disable 1: enable bit 2 lve : lvd interrupt control 0: disable 1: enable bit 1 ade : a/d converter interrupt control 0: disable 1: enable bit 0 iice : i 2 c interrupt control 0: disable 1: enable name pt ? 0af pt ? 0pf pt ? 0ae pt ? 0pe r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5 ptm0af : ptm0 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 ptm0pf : ptm0 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as 0 bit 1 ptm0ae : ptm0 comparator a match interrupt control 0: disable 1: enable bit 0 ptm0pe : ptm0 comparator p match interrupt control 0: disable 1: enable
rev. 1.00 10? ?a??? 0?? ?01? rev. 1.00 10 ? ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu mf eister bit 6 5 4 3 0 name pt ? 1af pt ? 1pf pt ? 1ae pt ? 1pe r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5 ptm1af : ptm1 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 ptm1pf : ptm1 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as 0 bit 1 ptm1ae : ptm1 comparator a match interrupt control 0: disable 1: enable bit 0 ptm1pe : ptm1 comparator p match interrupt control 0: disable 1: enable when the conditions for an interrupt event occur , such as a tm comparator p , comparator a match or a/d conversion completion etc., the relevant interrupt request fag will be set. whether the request fag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enabl e bit. if the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request fag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector . the global interrupt enable bit, if cleared to zero, will disable all interrupts. when an interrupt is generated, the program counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the corresponding interrupt vector . the microcontroller will then fetch its next instruction from this interrupt vector . the instruction at this vector will usually be a jmp which will jump to another section of program which is known as the interrupt service routine. here is located the code to control the appropriate interrupt. the interrupt service routine must be terminated with a "reti", which retrieves the original program counter address from the st ack a nd a llows t he m icrocontroller t o c ontinue wi th n ormal e xecution a t t he p oint wh ere t he interrupt occurred. the various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority . some interrupt sources have their own individual vector w hile others s hare the s ame multi-function interrupt vector . o nce an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, emi bit will be cleared automatically . this will prevent any further interrupt nesting from occurring. however, i f ot her i nterrupt re quests oc cur duri ng t his i nterval, a lthough t he i nterrupt wi ll not be immediately serviced, the request fag will still be recorded.
rev. 1.00 104 ? a ??? 0 ?? ? 01 ? rev. 1.00 105 ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu if an interrupt requires immediate servicing while the program is alread y in another interrupt service routine, the emi bit should be set after entering the routine, to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full. in case of simultaneous requests, the accompanying diagram shows the priority that is a pplied. al l o f t he i nterrupt r equest fa gs wh en se t wi ll wa ke-up t he d evice i f i t i s i n sl eep o r idle mode, however to prevent a wake-up from occurring the corresponding fag should be set before the device is in sleep or idle mode. inte??upt name request flags enable bits ?aste? enable ve?to? e?i auto disabled in isr p?io?ity hig? low inte??upts ?ontained wit?in ?ulti-fun?tion inte??upts xxe enable bits xxf request flag? auto ?eset in isr legend xxf request flag? no auto ?eset in isr ?. fun?t. 0 ?f0f ?f0e e?i e?i ?. fun?t. 1 ?f1f ?f1e 10h 14h pt?0 p pt?0pf pt?0pe pt?0 a pt?0af pt?0ae pt?1 p pt?1pf pt?1pe pt?1 a pt?1af pt?1ae 04h int0 pin int0f int0e e?i 0ch int1 pin int1f int1e e?i e?i 08h ocp ocpf ocpe time base 0 tb0f tb0e e?i 18h time base 1 tb1f tb1e e?i 1ch ?0h i ? c iicf iice e?i ?4h a/d adf ade e?i e?i lvd lvf lve ?8h eepro? def dee e?i ?ch inte??upt name request flags enable bits inte??upt st?u?tu?e exte?nal inte??upt the external interrupts are controlled by signal transitions on the pins int0~int1. an external interrupt request will take place when the external interrupt request fags, int0f~int1f , are set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pins . t o allow the program to branch to its res pective interrupt vector addres s, the g lobal i nterrupt e nable b it, e mi, a nd r espective e xternal i nterrupt e nable b it, i nt0e~int1e, must first be set. additionally the correct interrupt edge type mus t be selected using the integ register to enable the external interrupt function and to choose the trigger edge type. as the external interrupt pins are pin-shared with i/o pins, they can only be confgured as external interrupt pins if their external interrupt enable bit in the corresponding interrupt register has been set and the external interrupt pin is selected by the corresponding pin-shared function selection bits. the pin must also be setup as an input by setting the corresponding bit in the port control register . when the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector , will take place. when the interrupt is serviced, the
rev. 1.00 104 ?a??? 0?? ?01? rev. 1.00 105 ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu external interrupt request fags, int0f~int1f , will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. note that any pull-high resistor selections on the external interrupt pins will remain valid even if the pin is used as an external interrupt input. the integ re gister i s use d t o se lect t he t ype of a ctive e dge t hat wi ll t rigger t he e xternal i nterrupt. a choice of ei ther risi ng or fall ing or both edge types ca n be chosen to tri gger an ext ernal int errupt. note that the integ register can also be used to disable the external interrupt function. the ocp interrupt is controlled by detecting the ocp input current. an ocp interrupt request will take place when the ocp interrupt request fag, ocpf , is set, which occurs when a lar ge current is detected. t o allow the program to branch to its res pective interrupt vector address , the global interrupt enable bit, emi, and ocp interrupt enable bit, ocpe, must frst be set. when the interrupt is enabled , the stack is not full and an over current is detected, a subroutine call to the ocp interrupt vector, will take place. when the interrupt is serviced, the ocp interrupt flag, ocpf , will be automatically cleared. the emi bit will also be automatically cleared to disable other interrupts. the function of the t ime base interrupts is to provide regular time signal in the form of an internal interrupt. they are controlled by the overfow signals from their respective timer functions. when these happens their respective interrupt request flags, tb0f or tb1f will be set. t o allow the program to branch to their respective interrupt vector addresses, the global interrupt enable bit, emi and t ime base enable bits, tb0e or tb1e, must frst be set. when the interrupt is enabled, the stack is not full and the t ime base overfow s, a subroutine call to their res pective vector locations will take place. when the interrupt is serviced, the respective interrupt request fag, tb0f or tb1f , will be automatically reset and the emi bit will be cleared to disable other interrupts. the purpose of the t ime base interrupt is to provide an interrupt signal at fxed time periods. its clock source, f psc , originates from the internal clock source f sys , f sys /4 or f sub and then passes through a divider , the division ratio of which is selected by programming the appropriate bits in the tb0 c and tb 1 c registers to obtain longer interrupt periods whose value ranges. the clock source which i n t urn c ontrols t he t ime b ase i nterrupt p eriod i s se lected u sing t he clksel1~clksel0 bits in the psc r register. ? u x f sys /4 f sys f sub p?es?ale? clksel[1:0] f psc f psc /? 4 ~ f psc /? 11 ? u x ? u x tb0[?:0] tb1[?:0] time base 0 inte??upt time base 1 inte??upt tb0on tb1on f psc /? 8 ~ f psc /? 15 time base inte??upt
rev. 1.00 10 ? ? a ??? 0 ?? ? 01 ? rev. 1.00 107 ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu pc eister bit 6 5 4 3 0 name clksel1 clksel0 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 clksel1~clksel0 : prescaler clock source selection 00: 01: /4 1x : name tb0on tb0 ? tb01 tb00 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 tb0on : t ime base 0 control 0: disable 1: enable bit 6~3 unimplemented, read as 0 bit 2~0 tb02~tb00 : select t ime base 0 t ime-out period 000: 2 4 /f 001: 2 5 /f 010: 2 /f 011: 2 7 /f 100: 2 /f 101: 2 9 /f 110: 2 10 /f 111: 2 11 /f name tb1on tb1 ? tb11 tb10 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 tb1on : t ime base 1 control 0: disable 1: enable bit 6~3 unimplemented, read as 0 bit 2~0 tb12~tb10 : select t ime base 1 t ime-out period 000: 2 /f 001: 2 9 /f 010: 2 10 /f 011: 2 11 /f 100: 2 12 /f 101: 2 13 /f 110: 2 14 /f 111: 2 15 /f
rev. 1.00 10? ?a??? 0?? ?01? rev. 1.00 107 ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu c nterrt an i 2 c interrupt request will take place when the i 2 c interrupt request flag, iicf , is set, which occurs when a byte of data has been received or transmitted by the i 2 c interface, i 2 c address match or i 2 c time-o ut. t o all ow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and the serial interface interrupt enable bit, iice, must frst be set. when the interrupt is enabled, the stack is not full and any of these situations occurs, will take place. when the i 2 c interface interrupt is serviced, the interrupt request fag, iicf , will be automatically reset and the emi bit will be cleared to disable other interrupts. the a/d converter interrupt is controlled by the termination of an a/d conversion process. an a/d converter interrupt request will take place when the a/d converter interrupt request fag, adf , is set, which occurs when the a/d conversion process fnishes. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, a nd a/ d interrupt enable bit, ade, must frst be set. when the interrupt is enabled, the stack is not full and the a/d conversion process has ended, a subroutine call to the a/d converter interrupt vector , will take place. when the interrupt is serviced, the a/d converter interrupt fag, adf , will be automatically cleared. the emi bit will also be automatically cleared to disable other interrupts. an l vd interrupt reques t w ill take place w hen the l vd interrupt reques t f ag, l vf, is s et, w hich occurs when the low v oltage detector function detects a low power supply voltage. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and low v oltage interrupt enable bit, l ve, must frst be set. when the inte rrupt is enabled, the stack is not full and a low voltage condition occurs, a subroutine call to the l vd interrupt vector , will take place. when the low v oltage interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, and the lvd interrupt request fag, lvf, will be also automatically cleared. an eeprom interrupt request will take place when the eeprom interrupt request fag, def, is set, which occurs when an eeprom w rite cycle ends. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and eeprom interrupt enable bit, dee, must frst be set. when the interrupt is enabled, the stack is not full and an eeprom w rite cycle ends, a subroutine call to the respective eeprom interrupt vect or will take place. when the eeprom interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, and the eeprom interrupt request fag, def, will be also automatically cleared.
rev. 1.00 108 ? a ??? 0 ?? ? 01 ? rev. 1.00 109 ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu mlti-ntion nterrt within this device there are two multi-function interrupts. unlike the other independent interrupts, these int errupts have no i ndependent sourc e, but rat her are form ed from other exi sting i nterrupt sources, namely the tm interrupts. a multi-function interrupt request will take place when any of the multi-function interrupt request flags, mfnf are set. the multi-function interrupt flags will be set when any of their included functions generate an interrupt request fag. t o allow the program to branch to its respective interrupt vector address, when the multi-func tion interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of multi-function interrupt occurs, a subroutine call to one of the multi-function interrupt vectors will take place. when the interrupt is serviced, the related multi- function request fag will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. however, i t m ust be not ed t hat, a lthough t he mul ti-function int errupt fa gs wi ll be a utomatically reset when the interrupt is serviced, the request fags from the original source of the multi-function interrupts, namely the tm interrupts will not be automatically reset and must be manually reset by the application program. the periodic t ype tms have two interrupts. all of the tm interrupts are contained within the multi- function interrupts. for each of the periodic t ype tms there are two interrupt request fags ptmnpf and ptmnaf and two enable bits ptmnpe and ptmnae. a tm inte rrupt request will take place when any of the tm request fags are set, a situation which occurs when a tm comparator p or a match situation happens. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, respective tm interrupt enable bit, and relevant multi-function interrupt enable bit, mfne, must frst be set. when the interrupt is enabled, the stack is not full and a tm comparator match situation occurs, a subroutine call to the relevant multi-function interrupt vector locations, will take place. when the tm interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the related mfnf fag will be automatically cleared. as the tm interrupt request fags will not be automatically cleared, they have to be cleared by the application program. each of the int errupt funct ions has the capa bility of waki ng up the mi crocontroller when in the sleep or idle mode. a wake-up is generated when an interrupt request fag changes from low to high and is independent of whether the interrupt is enabled or not. therefore, even though the device is in the sleep or idle mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pins or a low power supply voltag e may cause their respective interrupt fag to be set high and consequently generate an interrupt. care must therefore be taken if spurious wake-up situations are to be avoided. if an interrupt wake-up function is to be disabled then the corresponding interrupt request fag should be set high before the device enters the sleep or idle mode. the interrupt enable bits have no effect on the interrupt wake-up function.
rev. 1.00 108 ?a??? 0?? ?01? rev. 1.00 109 ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu prorain consierations by di sabling t he re levant i nterrupt e nable bi ts, a re quested i nterrupt c an be pre vented from be ing serviced, however , once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request fag is cleared by the application program. where a certain interrupt is contained w ithin a m ulti-function interrupt, then w hen the interrupt service routine is executed, as only the multi-function interrupt request flags, mfnf , will be automatically cleared, the individual request flag for the function needs to be cleared by the application program. it is recommended that programs do not use the call instruction within the interrupt service subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately . if only one stack is left and the inte rrupt is not well controlled, the original control sequence will be damaged once a call subroutine is executed in the interrupt subroutine. every i nterrupt h as t he c apability o f wa king u p t he m icrocontroller wh en i t i s i n sl eep o r i dle mode, the wake up being generated when the interrupt request fag changes from low to high. if it is required to prevent a certain interru pt from waking up the microcontrol ler then its respective request fag should be frst set high before enter sleep or idle mode. as only the program counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator , status register or other registers are altered by the interrupt service program, t heir c ontents shoul d be sa ved t o t he m emory a t t he be ginning of t he i nterrupt se rvice routine. t o return from an interrupt subroutine, either a ret or reti instruction may be executed. the reti instruction in addition to executing a return to the main program also automatically sets the emi bit high to allow further interrupts. the ret instruction however only executes a return to the main program leaving the emi bit in its present zero state and therefore disabling the execution of further interrupts.
rev. 1.00 110 ? a ??? 0 ?? ? 01 ? rev. 1.00 111 ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu ow oltae etetor t he device has a low v oltage detector function, also known as l vd. this enabled the device to monitor the power supply voltage, v dd , and provide a warning signal should it fall below a certain level. this function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. the low v oltage detector also has the capability of generating an interrupt signal. the low voltage detector function is controlled using a single register with the name l vdc. three bits in this register , vl vd2~vlvd0, are used to select one of eight fxed voltages below which a l ow vo ltage c ondition wi ll be de termined. a l ow vo ltage c ondition i s i ndicated whe n t he l vdo bit is set. if the l vdo bit is low , this indicates that the v dd voltage is above the preset low voltage value. the l vden bit is used to control the overall on/of f function of the low voltage detector . setting the bit high will enable the low voltage detector . clearing the bit to zero will switch of f the internal low voltage detector circuits. as the low voltage detector will consume a certain amount of power, it may be desirable to switch of f the circuit when not in use, an important consideration in power sensitive battery powered applications. name lvdo lvden vbgen vlvd ? vlvd1 vlvd0 r/w r r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5 : lvd output flag 0: no low v oltage detect 1: low v oltage detect bit 4 : low v oltage detector control 0: disable 1: enable bit 3 : bandgap buffer control 0: disable 1: enable note that the bandgap circuit is enabled when the l vd or l vr functio n is enabled or when the vbgen bit is set to 1. bit 2~0 : select lvd v oltage 000: 2.0v 001: 2.2v 010: 2.4v 011: 2.7v 100: 3.0v 101: 3.3v 110: 3.6v 111: 4.0v
rev. 1.00 110 ?a??? 0?? ?01? rev. 1.00 111 ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu eration the low v oltage detector function operates by comparing the pow er supply voltage, v dd , with a pre-specifed volta ge level stored in the l vdc register . this has a range of between 2.0v and 4.0v . when the power supply voltage, v dd , falls below this pre-determined value, the l vdo bit will be set high indicating a low power supply voltage condition. the low v oltage detector function is supplied by a reference voltage which will be automatically enabled. when the device is in the sleep mode, the low voltage detector will be disabled even if the l vden bit is high. after enabling the low v oltage detector , a time delay t lvds should be allowed for the circuitry to stabilise before reading the l vdo bit. note also that as the v dd voltage may rise and fall rather slowly , at the voltage nears that of v lvd , there may be multiple bit lvdo transitions. vdd lvden lvdo v lvd t lvds lvd ope?ation the low v oltage detector also has its own interrupt, providing an alte rnative means of low voltage detection, in addit ion to polling the l vdo bit. the interrupt will only be generated after a delay of t lvd after the l vdo bit has been set high by a low voltage condition. when the device is powered down the low v oltage detector will remain active if the l vden bit is high. in this case, the l vf interrupt request fag will be set, causing an interrupt to be generated if v dd falls below the preset lvd v oltage. t his wi ll c ause t he d evice t o wa ke-up f rom t he sl eep o r i dle mo de, h owever i f the low v oltage detector wake up function is not required then the l vf fag should be frst set high before the device enters the sleep or idle mode. when l vd functi on is enabled, it is recommenced to clear l vd fag frst, and then enables interrupt function to avoid mistake action.
rev. 1.00 11 ? ? a ??? 0 ?? ? 01 ? rev. 1.00 11 ? ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu liation cirits a + - hv 5 vcc hvo h level: vcc l level: vss pb0/int1/ptp1 pb1/ptp1b pb2/sda pb3/sck 1 2 3 4 ldo 5v vdd vdd/avdd vss/avss/vssh pa0/icpda/an0/ptp0 pa1/ocpi/ptck0/ptp0b/an1 pa2/icpck/ptpi/an2 pa3/vref/an3 pa4/an4/int0 pa5/an5 pa6/ptck1/an6 pa7/ptp1i/an7 opa cmp int ocp(scp) integrated ocp(scp) dac ocpi 8 7 9 an0 10 11 12 13 14 15 16 an1 an2 an3 an4 an5 an6 an7 HT45F3630 16ssop 10 f 0.1f 10 ? b+ 8050 100 ? 11v 1 f~ 10 f 5v anx(internel) ocpi t an1 vdd battery temp. detection 0.1f 10k ? 0.1f 27k ? vdd an2 an3 battery voltage detection 0.1f 10k ? 2 ? b1 battery pack input + 22 ? hv 22 f 0.1f b+ b- t t b1
rev. 1.00 11 ? ?a??? 0?? ?01? rev. 1.00 11 ? ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu nstrtion et ntrotion central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that direc ts the microcontroller to perform certain operations. in the case of holtek microcontroller , a comprehensive and fexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. for easier understanding of the various instruction codes, they have been subdivided into several functional groupings. most instructions are implemented within one instruction cycle. the exceptions to this are branch, call, or table read instructions where two ins truction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator , most instructions would be i mplemented wi thin 0.5 s a nd bra nch or c all i nstructions woul d be i mplemented wi thin 1s. although instructions which require one more cycle to implement are generally limited to the jmp , call, ret , reti and table read instructions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to implement. as instructions which change the contents of the pcl will imply a direct j ump t o t hat ne w a ddress, one m ore c ycle wi ll be re quired. e xamples of suc h i nstructions would be "clr pcl" or "mov pcl, a". for the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. the t ransfer of da ta wi thin t he m icrocontroller progra m i s one of t he m ost fre quently use d operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specifc immediate data directly into the ac cumulator. one of t he m ost i mportant da ta t ransfer a pplications i s t o re ceive da ta from t he input ports and transfer data to the output ports. the ability to perform certain arithm etic operations and data manipula tion is a necessary feature of most m icrocontroller a pplications. w ithin t he hol tek m icrocontroller i nstruction se t a re a ra nge of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to ens ure correct handling of carry and borrow data w hen res ults exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specifed.
rev. 1.00 114 ? a ??? 0 ?? ? 01 ? rev. 1.00 115 ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu oial an otate eration the standard logical operations such as and, or, xor and cpl all have their own instruction within t he hol tek m icrocontroller i nstruction se t. as wi th t he c ase of m ost i nstructions i nvolving data m anipulation, d ata m ust p ass t hrough t he ac cumulator wh ich m ay i nvolve a dditional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. dif ferent rotate instructions exist depending on program requirements. rotate instructions are useful for serial port progra mming a pplications whe re da ta c an be rot ated from a n i nternal re gister i nto t he ca rry bit from where it can be examined and the necessary serial bit set high or low . another application which rotate data operations are used is to implement multiplication and division calculations. program branching takes the form of either jumps to specifed locations using the jmp instruction or t o a su broutine usi ng t he cal l i nstruction. t hey di ffer i n t he se nse t hat i n t he c ase of a subroutine call, the program mus t return to the ins truction immediately w hen the s ubroutine has been carried out. this is done by placing a return ins truction " ret" in the s ubroutine w hich w ill cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping of f point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is frst made regarding the c ondition of a c ertain da ta m emory or i ndividual bi ts. de pending upon t he c onditions, t he program will continue with the next instruction or skip over it and jump to the following instruction. these i nstructions a re t he ke y t o de cision m aking a nd bra nching wi thin t he progra m pe rhaps determined by the condition of certain input switches or by the condition of internal data bits. the abili ty to provide single bit operations on data memory is an extremely fexible feature of all holtek microcontrollers . this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the "set [m].i" or "clr [m]. i" instructions respectively . the feature removes the need for programmers to frst read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write process is take n care of automatically when these bit operation instructions are used. data st orage i s norm ally i mplemented by usi ng re gisters. however , whe n worki ng wi th l arge amounts of fxed data, the volume involved often makes it inconvenient to store the fxed data in the data memory . t o overcome this problem, holtek microcontrollers allow an area of program memory to be set as a table where data can be directly stored. a set of easy to use instructions provides the means by w hich this fixed data can be referenced and retrieved from the program memory. in addition to the above functional instructions, a range of other instructions also exist such as the "hal t" i nstruction f or po wer-down o perations a nd i nstructions t o c ontrol t he o peration o f the w atchdog t imer for reliable program operations under extreme electric or electromagnetic environments. for their relevant operations, refer to the functional related sections.
rev. 1.00 114 ?a??? 0?? ?01? rev. 1.00 115 ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu nstrtion et ar the i nstructions re lated t o t he da ta m emory a ccess i n t he fol lowing t able c an be used whe n t he desired data memory is located in data memory sector 0. x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address add a ? [m] add data ? emo ? y to acc 1 z ? c ? ac ? ov ? sc add ? a ? [m] add acc to data ? emo ? y 1 note z ? c ? ac ? ov ? sc add a ? x add immediate data to acc 1 z ? c ? ac ? ov ? sc adc a ? [m] add data ? emo ? y to acc wit ? ca ?? y 1 z ? c ? ac ? ov ? sc adc ? a ? [m] add acc to data memo ? y wit ? ca ?? y 1 note z ? c ? ac ? ov ? sc sub a ? x subt ? a ? t immediate data f ? om t ? e acc 1 z ? c ? ac ? ov ? sc ? cz sub a ? [m] subt ? a ? t data ? emo ? y f ? om acc 1 z ? c ? ac ? ov ? sc ? cz sub ? a ? [m] subt ? a ? t data ? emo ? y f ? om acc wit ? ? esult in data ? emo ? y 1 note z ? c ? ac ? ov ? sc ? cz sbc a ? x subt ? a ? t immediate data f ? om acc wit ? ca ?? y 1 z ? c ? ac ? ov ? sc ? cz sbc a ? [m] subt ? a ? t data ? emo ? y f ? om acc wit ? ca ?? y 1 z ? c ? ac ? ov ? sc ? cz sbc ? a ? [m] subt ? a ? t data ? emo ? y f ? om acc wit ? ca ?? y ? ? esult in data ? emo ? y 1 note z ? c ? ac ? ov ? sc ? cz daa [m] de ? imal adjust acc fo ? addition wit ? ? esult in data ? emo ? y 1 note c logi? ope?ation and a ? [m] logi ? al and data ? emo ? y to acc 1 z or a ? [m] logi ? al or data ? emo ? y to acc 1 z xor a ? [m] logi ? al xor data ? emo ? y to acc 1 z and ? a ? [m] logi ? al and acc to data ? emo ? y 1 note z or ? a ? [m] logi ? al or acc to data ? emo ? y 1 note z xor ? a ? [m] logi ? al xor acc to data ? emo ? y 1 note z and a ? x logi ? al and immediate data to acc 1 z or a ? x logi ? al or immediate data to acc 1 z xor a ? x logi ? al xor immediate data to acc 1 z cpl [m] complement data ? emo ? y 1 note z cpla [m] complement data ? emo ? y wit ? ? esult in acc 1 z in??ement & de??ement inca [m] in ?? ement data ? emo ? y wit ? ? esult in acc 1 z inc [m] in ?? ement data ? emo ? y 1 note z deca [m] de ?? ement data ? emo ? y wit ? ? esult in acc 1 z dec [m] de ?? ement data ? emo ? y 1 note z rotate rra [m] rotate data ? emo ? y ? ig ? t wit ? ? esult in acc 1 none rr [m] rotate data ? emo ? y ? ig ? t 1 note none rrca [m] rotate data ? emo ? y ? ig ? t t ?? oug ? ca ?? y wit ? ? esult in acc 1 c rrc [m] rotate data ? emo ? y ? ig ? t t ?? oug ? ca ?? y 1 note c rla [m] rotate data ? emo ? y left wit ? ? esult in acc 1 none rl [m] rotate data ? emo ? y left 1 note none rlca [m] rotate data ? emo ? y left t ?? oug ? ca ?? y wit ? ? esult in acc 1 c rlc [m] rotate data ? emo ? y left t ?? oug ? ca ?? y 1 note c
rev. 1.00 11 ? ? a ??? 0 ?? ? 01 ? rev. 1.00 117 ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu mneoni esrition cles fla ete ata moe ? ov a ? [m] ? ove data ? emo ? y to acc 1 none ? ov [m] ? a ? ove acc to data ? emo ? y 1 note none ? ov a ? x ? ove immediate data to acc 1 none bit ope?ation clr [m].i clea ? bit of data ? emo ? y 1 note none set [m].i set bit of data ? emo ? y 1 note none b?an?? ope?ation j ? p add ? jump un ? onditionally ? none sz [m] skip if data ? emo ? y is ze ? o 1 note none sza [m] skip if data ? emo ? y is ze ? o wit ? data movement to acc 1 note none sz [m].i skip if bit i of data ? emo ? y is ze ? o 1 note none snz [m] skip if data ? emo ? y is not ze ? o 1 note none snz [m].i skip if bit i of data ? emo ? y is not ze ? o 1 note none siz [m] skip if in ?? ement data ? emo ? y is ze ? o 1 note none sdz [m] skip if de ?? ement data ? emo ? y is ze ? o 1 note none siza [m] skip if in ?? ement data ? emo ? y is ze ? o wit ? ? esult in acc 1 note none sdza [m] skip if de ?? ement data ? emo ? y is ze ? o wit ? ? esult in acc 1 note none call add ? sub ? outine ? all ? none ret retu ? n f ? om sub ? outine ? none ret a ? x retu ? n f ? om sub ? outine and load immediate data to acc ? none reti retu ? n f ? om inte ?? upt ? none table read ope?ation tabrd [m] read table (specifc page) to tblh and data memory ? note none tabrdl [m] read table (last page) to tblh and data ? emo ? y ? note none itabrd [m] increment table pointer tblp frst and read table to tblh and data memory ? note none itabrdl [m] increment table pointer tblp frst and read table (last page) to tblh and data ? emo ? y ? note none ?is?ellaneous nop no ope ? ation 1 none clr [m] clea ? data ? emo ? y 1 note none set [m] set data ? emo ? y 1 note none clr wdt clea ? wat ?? dog time ? 1 to ? pdf swap [m] swap nibbles of data ? emo ? y 1 note none swapa [m] swap nibbles of data ? emo ? y wit ? ? esult in acc 1 none halt ente ? powe ? down mode 1 to ? pdf note: 1. for skip instructions, if the result of the comparison involves a skip then up to three cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the clr wdt instruction the t o and pdf fags may be af fected by the execution status. the t o and pdf fags are cleared after the clr wdt instructions is executed. otherwise the t o and pdf fags remain unchanged.
rev. 1.00 11 ? ?a??? 0?? ?01? rev. 1.00 117 ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu tene nstrtion et the extended instructions are used to support the full range address access for the data memory . when the accessed data memory is located in any data memory sections except sector 0, the extended instructi on can be used to access the data memory instead of using the indirect addressing access to improve the cpu frmware performance. ladd a ? [m] add data ? emo ? y to acc ? z ? c ? ac ? ov ? sc ladd ? a ? [m] add acc to data ? emo ? y ? note z ? c ? ac ? ov ? sc ladc a ? [m] add data ? emo ? y to acc wit ? ca ?? y ? z ? c ? ac ? ov ? sc ladc ? a ? [m] add acc to data memo ? y wit ? ca ?? y ? note z ? c ? ac ? ov ? sc lsub a ? [m] subt ? a ? t data ? emo ? y f ? om acc ? z ? c ? ac ? ov ? sc ? cz lsub ? a ? [m] subt ? a ? t data ? emo ? y f ? om acc wit ? ? esult in data ? emo ? y ? note z ? c ? ac ? ov ? sc ? cz lsbc a ? [m] subt ? a ? t data ? emo ? y f ? om acc wit ? ca ?? y ? z ? c ? ac ? ov ? sc ? cz lsbc ? a ? [m] subt ? a ? t data ? emo ? y f ? om acc wit ? ca ?? y ? ? esult in data ? emo ? y ? note z ? c ? ac ? ov ? sc ? cz ldaa [m] de ? imal adjust acc fo ? addition wit ? ? esult in data ? emo ? y ? note c logi? ope?ation land a ? [m] logi ? al and data ? emo ? y to acc ? z lor a ? [m] logi ? al or data ? emo ? y to acc ? z lxor a ? [m] logi ? al xor data ? emo ? y to acc ? z land ? a ? [m] logi ? al and acc to data ? emo ? y ? note z lor ? a ? [m] logi ? al or acc to data ? emo ? y ? note z lxor ? a ? [m] logi ? al xor acc to data ? emo ? y ? note z lcpl [m] complement data ? emo ? y ? note z lcpla [m] complement data ? emo ? y wit ? ? esult in acc ? z in??ement & de??ement linca [m] in ?? ement data ? emo ? y wit ? ? esult in acc ? z linc [m] in ?? ement data ? emo ? y ? note z ldeca [m] de ?? ement data ? emo ? y wit ? ? esult in acc ? z ldec [m] de ?? ement data ? emo ? y ? note z rotate lrra [m] rotate data ? emo ? y ? ig ? t wit ? ? esult in acc ? none lrr [m] rotate data ? emo ? y ? ig ? t ? note none lrrca [m] rotate data ? emo ? y ? ig ? t t ?? oug ? ca ?? y wit ? ? esult in acc ? c lrrc [m] rotate data ? emo ? y ? ig ? t t ?? oug ? ca ?? y ? note c lrla [m] rotate data ? emo ? y left wit ? ? esult in acc ? none lrl [m] rotate data ? emo ? y left ? note none lrlca [m] rotate data ? emo ? y left t ?? oug ? ca ?? y wit ? ? esult in acc ? c lrlc [m] rotate data ? emo ? y left t ?? oug ? ca ?? y ? note c data ?ove l ? ov a ? [m] ? ove data ? emo ? y to acc ? none l ? ov [m] ? a ? ove acc to data ? emo ? y ? note none bit ope?ation lclr [m].i clea ? bit of data ? emo ? y ? note none lset [m].i set bit of data ? emo ? y ? note none
rev. 1.00 118 ? a ??? 0 ?? ? 01 ? rev. 1.00 119 ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu mneoni esrition cles fla ete branh lsz [m] skip if data ? emo ? y is ze ? o ? note none lsza [m] skip if data ? emo ? y is ze ? o wit ? data movement to acc ? note none lsnz [m] skip if data ? emo ? y is not ze ? o ? note none lsz [m].i skip if bit i of data ? emo ? y is ze ? o ? note none lsnz [m].i skip if bit i of data ? emo ? y is not ze ? o ? note none lsiz [m] skip if in ?? ement data ? emo ? y is ze ? o ? note none lsdz [m] skip if de ?? ement data ? emo ? y is ze ? o ? note none lsiza [m] skip if in ?? ement data ? emo ? y is ze ? o wit ? ? esult in acc ? note none lsdza [m] skip if de ?? ement data ? emo ? y is ze ? o wit ? ? esult in acc ? note none table read ltabrd [m] read table to tblh and data ? emo ? y ? note none ltabrdl [m] read table (last page) to tblh and data ? emo ? y ? note none litabrd [m] increment table pointer tblp frst and read table to tblh and data memory ? note none litabrdl [m] increment table pointer tblp frst and read table (last page) to tblh and data ? emo ? y ? note none ?is?ellaneous lclr [m] clea ? data ? emo ? y ? note none lset [m] set data ? emo ? y ? note none lswap [m] swap nibbles of data ? emo ? y ? note none lswapa [m] swap nibbles of data ? emo ? y wit ? ? esult in acc ? none note: 1. for these extended skip instructions, if the result of the comparison involves a skip then up to four cycles are required, if no skip takes place two cycles is required. 2. any extended instruction which changes the contents of the pcl register will also require three cycles for execution.
rev. 1.00 118 ?a??? 0?? ?01? rev. 1.00 119 ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu instruction defnition add d ata m emory to a cc w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] + c affected f ag(s) ov, z , a c, c , s c add a cc to d ata m emory w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] + c affected f ag(s) ov, z , a c, c , s c add d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] affected f ag(s) ov, z , a c, c , s c add im mediate data to a cc description the c ontents o f t he a ccumulator a nd t he s pecifed im mediate data a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + x affected f ag(s) ov, z , a c, c , s c add a cc to d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] affected f ag(s) ov, z , a c, c , s c logical a nd d ata m emory t o a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he a ccumulator. operation acc a cc a nd [ m] affected f ag(s) z logical a nd im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b it w ise l ogical a nd operation. t he re sult is s tored in t he a ccumulator. operation acc a cc a nd x affected f ag(s) z logical a nd a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc and [ m] affected f ag(s) z
rev. 1.00 1 ? 0 ? a ??? 0 ?? ? 01 ? rev. 1.00 1?1 ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu c ar subroutine c all description unconditionally c alls a s ubroutine a t t he s pecifed a ddress. th e p rogram c ounter t hen increments b y 1 to o btain t he a ddress o f t he n ext i nstruction w hich i s t hen p ushed o nto t he stack. t he sp ecifed a ddress is t hen loaded a nd t he p rogram c ontinues e xecution f rom t his new a ddress. a s t his instruction re quires a n a dditional op eration, it is a t wo c ycle instruction. operation stack p rogram counter + 1 program c ounter a ddr affected f ag(s) none clear d ata m emory description each b it o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m] 00h affected f ag(s) none clear bi t o f d ata m emory description bit i o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m].i 0 affected f ag(s) none clear w atchdog t imer description the t o, p df f ags a nd t he w dt a re al l c leared. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df complement d ata m emory description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. operation [m] [m] affected f ag(s) z complement d ata m emory w ith r esult i n a cc description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. th e c omplemented r esult i s s tored i n the a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] affected f ag(s) z decimal-adjust a cc f or addition w ith r esult i n d ata m emory description convert t he c ontents o f t he a ccumulator v alue to a b cd ( binary c oded d ecimal) v alue resulting f rom t he p revious a ddition o f t wo b cd v ariables. i f t he low n ibble is greater t han 9 or i f a c f ag i s s et, t hen a v alue o f 6 w ill b e a dded to t he l ow n ibble. o therwise t he l ow n ibble remains u nchanged. i f t he h igh n ibble i s g reater t han 9 o r i f t he c f ag i s s et, t hen a v alue o f 6 will b e a dded to t he h igh n ibble. e ssentially, t he decimal c onversion i s p erformed b y a dding 00h, 0 6h, 6 0h o r 6 6h depending o n t he a ccumulator a nd f ag c onditions. o nly t he c f ag may b e a ffected b y t his instruction w hich indicates t hat if t he o riginal b cd s um is greater t han 100, it al lows m ultiple p recision decimal a ddition. operation [m] a cc + 00h or [m] a cc + 06 h o r [m] a cc + 60h o r [m] a cc + 66h affected f ag(s) c
rev. 1.00 1?0 ?a??? 0?? ?01? rev. 1.00 1 ? 1 ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu c decrement d ata m emory description data i n t he s pecifed d ata m emory i s d ecremented b y 1 . operation [m] [ m] ? 1 affected f ag(s) z decrement d ata m emory wi th r esult i n a cc description data in t he sp ecifed d ata m emory is d ecremented b y 1 . t he re sult is s tored in t he accumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] ? 1 affected f ag(s) z enter p ower down m ode description this i nstruction s tops t he p rogram e xecution a nd t urns o ff t he s ystem c lock. th e c ontents o f the d ata m emory a nd r egisters a re r etained. th e w dt a nd p rescaler a re c leared. th e p ower down f ag p df i s s et a nd t he w dt t ime-out f ag t o i s c leared. operation to 0 pdf 1 affected f ag(s) to, p df increment d ata m emory description data in t he sp ecifed d ata m emory is incremented b y 1 . operation [m] [ m] + 1 affected f ag(s) z increment d ata m emory wi th r esult i n a cc description data i n t he sp ecifed d ata m emory i s i ncremented b y 1 . th e re sult i s s tored i n t he a ccumulator. the c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] + 1 affected f ag(s) z jump u nconditionally description the c ontents o f t he p rogram c ounter a re re placed w ith t he sp ecifed a ddress. p rogram execution t hen c ontinues f rom t his n ew a ddress. a s t his re quires t he insertion o f a d ummy instruction w hile t he n ew a ddress is loaded, it is a t wo c ycle instruction. operation program counter addr affected f ag(s) none move d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. operation acc [ m] affected f ag(s) none move im mediate data to a cc description the im mediate data s pecifed i s l oaded i nto t he a ccumulator. operation acc x affected f ag(s) none move a cc to d ata m emory description the c ontents o f t he a ccumulator a re c opied to t he s pecifed d ata m emory. operation [m] a cc affected f ag(s) none
rev. 1.00 1 ?? ? a ??? 0 ?? ? 01 ? rev. 1.00 1?? ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu p no o peration description no o peration i s p erformed. e xecution c ontinues w ith t he n ext i nstruction. operation no operation affected f ag(s) none logical o r d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise logical o r op eration. t he re sult is s tored in t he a ccumulator. operation acc a cc or [ m] affected f ag(s) z logical or im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b itwise l ogical o r operation. t he re sult is s tored in t he a ccumulator. operation acc a cc or x affected f ag(s) z logical or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical o r operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc or [ m] affected f ag(s) z return from s ubroutine description the p rogram c ounter is re stored f rom t he s tack. p rogram e xecution c ontinues a t t he re stored a ddress. operation program counter s tack affected f ag(s) none return f rom su broutine and l oad im mediate data to a cc description the p rogram c ounter i s r estored f rom t he s tack a nd t he a ccumulator l oaded w ith t he s pecifed immediate data. p rogram e xecution c ontinues a t t he r estored a ddress. operation program counter s tack acc x affected f ag(s) none return from i nterrupt description the p rogram c ounter is re stored f rom t he s tack a nd t he interrupts a re re -enabled b y s etting t he emi b it. e mi i s t he m aster i nterrupt g lobal e nable b it. i f a n i nterrupt w as p ending w hen t he reti instruction is e xecuted, t he p ending in terrupt ro utine w ill b e p rocessed b efore re turning to t he m ain p rogram. operation program counter s tack emi 1 affected f ag(s) none rotate d ata m emory l eft description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i=0~6) [m].0 [ m].7 affected f ag(s) none
rev. 1.00 1?? ?a??? 0?? ?01? rev. 1.00 1 ?? ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu rotate d ata m emory left w ith re sult in a cc description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . the r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i=0~6) acc.0 [ m].7 affected f ag(s) none rotate d ata m emory l eft t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated l eft b y 1 b it. b it 7 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i=0~6) [m].0 c c [ m].7 affected f ag(s) c rotate d ata m emory left t hrough c arry w ith re sult in a cc description data i n t he s pecifed d ata m emory and t he carry f ag are r otated l eft b y 1 b it. b it 7 r eplaces t he carry b it a nd t he o riginal c arry f ag i s r otated i nto t he b it 0 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i=0~6) acc.0 c c [ m].7 affected f ag(s) c rotate d ata m emory r ight description the contents of t he s pecifed d ata m emory are r otated r ight b y 1 b it w ith b it 0 r otated i nto b it 7 . operation [m].i [ m].(i+1); (i=0~6) [m].7 [ m].0 affected f ag(s) none rotate d ata m emory right with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it w ith b it 0 rotated i nto b it 7 . th e r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he data m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 [ m].0 affected f ag(s) none rotate d ata m emory r ight t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . operation [m].i [ m].(i+1); (i=0~6) [m].7 c c [ m].0 affected f ag(s) c
rev. 1.00 1 ? 4 ? a ??? 0 ?? ? 01 ? rev. 1.00 1?5 ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu c rotate d ata m emory right th rough c arry with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 r eplaces the c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 c c [ m].0 affected f ag(s) c subtract d ata m emory from a cc wi th c arry description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he a ccumulator. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] ? c affected f ag(s) ov, z , a c, c , s c, c z subtract im mediate data f rom a cc w ith carry description the immediate da ta a nd t he c omplement o f t he c arry f ag a re s ubtracted f rom t he accumulator. t he re sult is s tored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is negative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is p ositive o r z ero, t he c f ag will be se t t o 1 . operation acc a cc - [ m] - c affected f ag(s) ov, z , ac , c , s c, cz subtract d ata m emory from a cc wi th c arry a nd r esult i n d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he d ata m emory. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] ? c affected f ag(s) ov, z , a c, c , s c, c z skip i f decrement d ata m emory i s 0 description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] ? 1 skip if [ m]=0 affected f ag(s) none skip i f decrement d ata m emory i s z ero w ith r esult i n a cc description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he r esult is n ot 0 , the p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] ? 1 skip if a cc=0 affected f ag(s) none
rev. 1.00 1?4 ?a??? 0?? ?01? rev. 1.00 1 ? 5 ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu t set d ata m emory description each b it o f t he s pecifed d ata m emory i s s et t o 1 . operation [m] f fh affected f ag(s) none set b it o f d ata m emory description bit i o f t he s pecifed d ata m emory i s s et t o 1 . operation [m].i 1 affected f ag(s) none skip i f i ncrement d ata m emory i s 0 description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] + 1 skip if [ m]=0 affected f ag(s) none skip if increment d ata m emory is z ero w ith re sult in a cc description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] + 1 skip if a cc=0 affected f ag(s) none skip i f d ata m emory i s no t 0 description if t he sp ecifed d ata m emory is n ot 0 , t he f ollowing instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip i f [ m].i 0 affected f ag(s) none skip i f d ata m emory i s no t 0 description if t he sp ecifed d ata m emory is n ot 0 , t he f ollowing instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip i f [ m] 0 affected f ag(s) none subtract d ata m emory from a cc description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] affected f ag(s) ov, z , a c, c , s c, c z
rev. 1.00 1 ?? ? a ??? 0 ?? ? 01 ? rev. 1.00 1?7 ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu ubm subtract d ata m emory from a cc wi th r esult i n d ata m emory description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he d ata m emory. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] affected f ag(s) ov, z , a c, c , s c, c z subtract im mediate data f rom a cc description the im mediate data s pecifed b y t he c ode i s s ubtracted f rom t he c ontents o f t he a ccumulator. the re sult is s tored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c fag w ill b e c leared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? x affected f ag(s) ov, z , a c, c , s c, c z swap ni bbles of d ata m emory description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. operation [m].3~[m].0 ? [ m].7~[m].4 affected f ag(s) none swap ni bbles of d ata m emory w ith r esult i n a cc description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. th e result i s s tored i n t he a ccumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc.3~acc.0 [ m].7~[m].4 acc.7~acc.4 [ m].3~[m].0 affected f ag(s) none skip i f d ata m emory i s 0 description if t he contents of t he s pecifed d ata m emory i s 0, t he following i nstruction i s s kipped. a s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m]=0 affected f ag(s) none skip i f d ata m emory i s 0 w ith data m ovement to a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. i f t he v alue i s z ero, the f ollowing instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction while t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he program p roceeds w ith t he f ollowing instruction. operation acc [ m] skip if [ m]=0 affected f ag(s) none skip i f b it i of d ata m emory i s 0 description if b it i o f t he sp ecifed d ata m emory is 0 , t he f ollowing instruction is s kipped. a s t his re quires the insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 , t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m].i=0 affected f ag(s) none
rev. 1.00 1?? ?a??? 0?? ?01? rev. 1.00 1 ? 7 ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu tb read ta ble ( specifc p age) to t blh a nd d ata m emory description the low b yte o f t he p rogram c ode ( specifc p age) a ddressed b y t he t able p ointer p air (tblp a nd t bhp) i s mo ved t o t he s pecifed d ata m emory a nd t he h igh by te mo ved t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none read t able (last p age) t o t blh a nd d ata m emory description the l ow by te o f t he pr ogram c ode (last p age) a ddressed by t he t able p ointer (tblp) i s mo ved to t he s pecifed d ata m emory a nd t he h igh b yte m oved to t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none increment ta ble p ointer l ow b yte fr st and r ead ta ble to t blh and d ata m emory description increment ta ble p ointer l ow b yte, t blp, fr st and t hen t he p rogram code addressed b y t he table p ointer ( tbhp and t blp) i s m oved to t he s pecifed d ata m emory and t he hi gh b yte moved t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none increment t able p ointer l ow by te f rst a nd r ead t able (last p age) t o t blh a nd d ata m emory description increment ta ble p ointer l ow b yte, t blp, fr st and t hen t he l ow b yte of t he p rogram code (last p age) addressed b y t he ta ble p ointer ( tblp) i s m oved to t he s pecifed d ata m emory and the h igh by te mov ed t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none logical x or d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or [ m] affected f ag(s) z logical x or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical x or operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc xor [ m] affected f ag(s) z logical x or im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or x affected f ag(s) z
rev. 1.00 1 ? 8 ? a ??? 0 ?? ? 01 ? rev. 1.00 1?9 ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu extended instruction defnition the extended instructions are used to directly access the data stored in any data memory sections. add d ata m emory to a cc w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] + c affected f ag(s) ov, z , a c, c , s c add a cc to d ata m emory w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] + c affected f ag(s) ov, z , a c, c , s c add d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] affected f ag(s) ov, z , a c, c , s c add a cc to d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] affected f ag(s) ov, z , a c, c , s c logical a nd d ata m emory t o a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he a ccumulator. operation acc a cc a nd [ m] affected f ag(s) z logical a nd a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc and [ m] affected f ag(s) z clear d ata m emory description each b it o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m] 00h affected f ag(s) none clear bi t o f d ata m emory description bit i o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m].i 0 affected f ag(s) none
rev. 1.00 1?8 ?a??? 0?? ?01? rev. 1.00 1 ? 9 ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu cp complement d ata m emory description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. operation [m] [m] affected f ag(s) z complement d ata m emory w ith r esult i n a cc description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. th e c omplemented r esult i s s tored i n the a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] affected f ag(s) z decimal-adjust a cc f or addition w ith r esult i n d ata m emory description convert t he c ontents o f t he a ccumulator v alue to a b cd ( binary c oded d ecimal) v alue resulting f rom t he p revious a ddition o f t wo b cd v ariables. i f t he low n ibble is greater t han 9 or i f a c f ag i s s et, t hen a v alue o f 6 w ill b e a dded to t he l ow n ibble. o therwise t he l ow n ibble remains u nchanged. i f t he h igh n ibble i s g reater t han 9 o r i f t he c f ag i s s et, t hen a v alue o f 6 will b e a dded to t he h igh n ibble. e ssentially, t he decimal c onversion i s p erformed b y a dding 00h, 0 6h, 6 0h o r 6 6h depending o n t he a ccumulator a nd f ag c onditions. o nly t he c f ag may b e a ffected b y t his instruction w hich indicates t hat if t he o riginal b cd s um is greater t han 100, it al lows m ultiple p recision decimal a ddition. operation [m] a cc + 00h or [m] a cc + 06 h o r [m] a cc + 60h o r [m] a cc + 66h affected f ag(s) c decrement d ata m emory description data i n t he s pecifed d ata m emory i s d ecremented b y 1 . operation [m] [ m] ? 1 affected f ag(s) z decrement d ata m emory wi th r esult i n a cc description data in t he sp ecifed d ata m emory is d ecremented b y 1 . t he re sult is s tored in t he accumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] ? 1 affected f ag(s) z increment d ata m emory description data in t he sp ecifed d ata m emory is incremented b y 1 . operation [m] [ m] + 1 affected f ag(s) z increment d ata m emory wi th r esult i n a cc description data i n t he sp ecifed d ata m emory i s i ncremented b y 1 . th e re sult i s s tored i n t he a ccumulator. the c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] + 1 affected f ag(s) z
rev. 1.00 1 ? 0 ? a ??? 0 ?? ? 01 ? rev. 1.00 1?1 ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu m move d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. operation acc [ m] affected f ag(s) none move a cc to d ata m emory description the c ontents o f t he a ccumulator a re c opied to t he s pecifed d ata m emory. operation [m] a cc affected f ag(s) none logical o r d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise logical o r op eration. t he re sult is s tored in t he a ccumulator. operation acc a cc or [ m] affected f ag(s) z logical or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical o r operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc or [ m] affected f ag(s) z rotate d ata m emory l eft description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i=0~6) [m].0 [ m].7 affected f ag(s) none rotate d ata m emory left w ith re sult in a cc description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . the r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i=0~6) acc.0 [ m].7 affected f ag(s) none rotate d ata m emory l eft t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated l eft b y 1 b it. b it 7 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i=0~6) [m].0 c c [ m].7 affected f ag(s) c rotate d ata m emory left t hrough c arry w ith re sult in a cc description data i n t he s pecifed d ata m emory and t he carry f ag are r otated l eft b y 1 b it. b it 7 r eplaces t he carry b it a nd t he o riginal c arry f ag i s r otated i nto t he b it 0 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i=0~6) acc.0 c c [ m].7 affected f ag(s) c
rev. 1.00 1?0 ?a??? 0?? ?01? rev. 1.00 1 ? 1 ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu rotate d ata m emory r ight description the contents of t he s pecifed d ata m emory are r otated r ight b y 1 b it w ith b it 0 r otated i nto b it 7 . operation [m].i [ m].(i+1); (i=0~6) [m].7 [ m].0 affected f ag(s) none rotate d ata m emory right with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it w ith b it 0 rotated i nto b it 7 . th e r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he data m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 [ m].0 affected f ag(s) none rotate d ata m emory r ight t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . operation [m].i [ m].(i+1); (i=0~6) [m].7 c c [ m].0 affected f ag(s) c rotate d ata m emory right th rough c arry with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 r eplaces the c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 c c [ m].0 affected f ag(s) c subtract d ata m emory from a cc wi th c arry description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he a ccumulator. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] ? c affected f ag(s) ov, z , a c, c , s c, c z subtract d ata m emory from a cc wi th c arry a nd r esult i n d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he d ata m emory. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] ? c affected f ag(s) ov, z , a c, c , s c, c z
rev. 1.00 1 ?? ? a ??? 0 ?? ? 01 ? rev. 1.00 1?? ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu skip i f decrement d ata m emory i s 0 description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] ? 1 skip if [ m]=0 affected f ag(s) none skip i f decrement d ata m emory i s z ero w ith r esult i n a cc description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he r esult is n ot 0 , the p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] ? 1 skip if a cc=0 affected f ag(s) none set d ata m emory description each b it o f t he s pecifed d ata m emory i s s et t o 1 . operation [m] f fh affected f ag(s) none set b it o f d ata m emory description bit i o f t he s pecifed d ata m emory i s s et t o 1 . operation [m].i 1 affected f ag(s) none skip i f i ncrement d ata m emory i s 0 description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] + 1 skip if [ m]=0 affected f ag(s) none skip if increment d ata m emory is z ero w ith re sult in a cc description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] + 1 skip if a cc=0 affected f ag(s) none skip i f d ata m emory i s no t 0 description if t he sp ecifed d ata m emory is n ot 0 , t he f ollowing instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip i f [ m].i 0 affected f ag(s) none
rev. 1.00 1?? ?a??? 0?? ?01? rev. 1.00 1 ?? ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu skip i f d ata m emory i s no t 0 description if t he c ontent o f t he sp ecifed d ata m emory is n ot 0 , t he f ollowing instruction is s kipped. a s this re quires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a two c ycle instruction. i f t he re sult is 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip i f [ m] 0 affected f ag(s) none subtract d ata m emory from a cc description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] affected f ag(s) ov, z , a c, c , s c, c z subtract d ata m emory from a cc wi th r esult i n d ata m emory description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he d ata m emory. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] affected f ag(s) ov, z , a c, c , s c, c z swap ni bbles of d ata m emory description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. operation [m].3~[m].0 ? [ m].7~[m].4 affected f ag(s) none swap ni bbles of d ata m emory w ith r esult i n a cc description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. th e result i s s tored i n t he a ccumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc.3~acc.0 [ m].7~[m].4 acc.7~acc.4 [ m].3~[m].0 affected f ag(s) none skip i f d ata m emory i s 0 description if t he contents of t he s pecifed d ata m emory i s 0, t he following i nstruction i s s kipped. a s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m]=0 affected f ag(s) none skip i f d ata m emory i s 0 w ith data m ovement to a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. i f t he v alue i s z ero, the f ollowing instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction while t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he program p roceeds w ith t he f ollowing instruction. operation acc [ m] skip if [ m]=0 affected f ag(s) none
rev. 1.00 1 ? 4 ? a ??? 0 ?? ? 01 ? rev. 1.00 1?5 ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu i skip i f b it i of d ata m emory i s 0 description if b it i o f t he sp ecifed d ata m emory is 0 , t he f ollowing instruction is s kipped. a s t his re quires the insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 , t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m].i=0 affected f ag(s) none read ta ble ( current p age) to t blh a nd d ata m emory description the low b yte o f t he p rogram c ode ( current p age) a ddressed b y t he t able p ointer ( tblp) is moved t o t he s pecifed d ata m emory a nd t he h igh by te mo ved t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none read t able (last p age) t o t blh a nd d ata m emory description the l ow by te o f t he pr ogram c ode (last p age) a ddressed by t he t able p ointer (tblp) i s mo ved to t he s pecifed d ata m emory a nd t he h igh b yte m oved to t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none increment ta ble p ointer l ow b yte fr st and r ead ta ble to t blh and d ata m emory description increment ta ble p ointer l ow b yte, t blp, fr st and t hen t he p rogram code addressed b y t he table p ointer ( tbhp and t blp) i s m oved to t he s pecifed d ata m emory and t he hi gh b yte moved t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none increment t able p ointer l ow by te f rst a nd r ead t able (last p age) t o t blh a nd d ata m emory description increment ta ble p ointer l ow b yte, t blp, fr st and t hen t he l ow b yte of t he p rogram code (last p age) addressed b y t he ta ble p ointer ( tblp) i s m oved to t he s pecifed d ata m emory and the h igh by te mov ed t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none logical x or d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or [ m] affected f ag(s) z logical x or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical x or operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc xor [ m] affected f ag(s) z
rev. 1.00 1?4 ?a??? 0?? ?01? rev. 1.00 1 ? 5 ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu paae noration note that the package information provided here is for consultation purposes only. as this information may be updated at regular intervals users are reminded to consult the holtek website for the latest version of the package/carton information . additional supplementary information with regard to packaging is listed below. click on the relevant section to be transferred to the relevant website page. ? package information (include outline dimensions, product tape and reel specifcations) ? the operation instruction of packing materials ? carton information
rev. 1.00 1 ?? ? a ??? 0 ?? ? 01 ? rev. 1.00 1?7 ?a??? 0?? ?01? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu 6-in p 50il tline iensions symbol dimensions in inch min. nom. max. a 0. ??? bsc b 0.154 bsc c 0.008 0.01 ? c 0.19 ? bsc d 0.0 ? 9 e 0.0 ? 5 bsc f 0.004 0.010 g 0.01 ? 0.050 h 0.004 0.010 0 8 symbol dimensions in mm ?in. nom. ?ax. a ? .000 bsc b ? .900 bsc c 0. ? 0 0. ? 0 c 4.900 bsc d 1.75 e 0. ?? 5 bsc f 0.10 0. ? 5 g 0.41 1. ? 7 h 0.10 0. ? 5 0 8
rev. 1.00 1?? ?a??? 0?? ?01? rev. 1.00 1 ? 7 ? a ??? 0 ?? ? 01 ? HT45F3630 power tool controller 8-bit flash mcu HT45F3630 power tool controller 8-bit flash mcu copy ? ig ? t ? ? 01 ? by holtek se ? iconductor inc. t ? e info ? mation appea ? ing in t ? is data s ? eet is believed to be a ?? u ? ate at t ? e time of publi ? ation. howeve ?? holtek assumes no ? esponsibility a ? ising f ? om t ? e use of the specifcations described. the applications mentioned herein are used solely fo ? t ? e pu ? pose of illust ? ation and holtek makes no wa ?? anty o ? ? ep ? esentation t ? at su ?? appli ? ations will be suitable wit ? out fu ? t ? e ? modifi ? ation ? no ? ? e ? ommends t ? e use of its p ? odu ? ts fo ? appli ? ation t ? at may p ? esent a ? isk to ? uman life due to malfun ? tion o ? ot ? e ? wise. holtek's p ? odu ? ts a ? e not aut ? o ? ized fo ? use as ?? iti ? al ? omponents in life suppo ? t devi ? es o ? systems. holtek ? ese ? ves t ? e ? ig ? t to alte ? its products without prior notifcation. for the most up-to-date information, please visit ou ? web site at ? ttp://www. ? oltek. ? om.tw.

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